Patents by Inventor Yen-Ting Lin

Yen-Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260177897
    Abstract: Disclosed is a projection device, including a light source module, an optical engine module and a lens module. The optical engine module includes a housing, a heatsink and a transmissive light valve, a light guide component and a light guide cover disposed inside the housing. The illumination beam provided by the light source module is transmitted in the light guide component and to the transmissive light valve. The light guide cover has a body and a heat dissipation opening. The body wraps the surrounding surface of the light guide component, while the heat dissipation opening exposes part of the surrounding surface of the light guide component. The heatsink includes a connecting part and a heatsink fin part. The first end of the connecting part is disposed in the heat dissipation opening of the light guide cover. The second end of the connecting part is connected to the heatsink fin part.
    Type: Application
    Filed: November 12, 2025
    Publication date: June 25, 2026
    Applicant: Coretronic Corporation
    Inventors: Wei-Min Chien, Yen-Ting Lin
  • Publication number: 20260170236
    Abstract: Disclosed are apparatuses, systems, and techniques implementing a language error correction system that leverages shared expertise of an ensemble of editor models. The techniques include processing, using a router network, an input representation of a text generated using text generation tool(s) to obtain an ensemble of scores, an individual score characterizing a degree of correspondence of the text to a field of expertise of a respective editor model of the ensemble. The techniques further include processing, using a plurality of editor models of the ensemble, the input representation of the text to generate a plurality of output representations of the text. The techniques further include generating a final representation of the text using a weighted combination of the plurality of output representations of the text, an individual output representation weighted using a score, of the ensemble of scores, obtained for a respective editor model of the plurality of editor models.
    Type: Application
    Filed: December 18, 2024
    Publication date: June 18, 2026
    Inventors: Chao-Han Huck Yang, Yen-Ting Lin, Zhehuai Chen, Piotr Zelasko, Xuesong Yang, Venkata Naga Krishna Chaitanya Puvvada, Szu-Wei Fu, Ke Hu, Jagadeesh Balam, Boris Ginsburg, Yu-Chiang Frank Wang
  • Patent number: 12607917
    Abstract: A projection device includes a shell, a lens, two first ribs, two second ribs, and a sliding cover. The shell has a top plate, a left sidewall, and a right sidewall, the top plate is respectively connected to the left sidewall and the right sidewall, and the top plate has an opening. The lens is disposed in the shell and exposed by the opening. The two first ribs are disposed on the top plate, extending directions of the two first ribs are perpendicular to the left sidewall and the right sidewall, and the opening is disposed between the two first ribs. The sliding cover is slidably disposed on the shell for covering the opening. The two second ribs are disposed on a top cover body of the sliding cover, and one of the two second ribs is located between the two first ribs.
    Type: Grant
    Filed: October 24, 2023
    Date of Patent: April 21, 2026
    Assignee: Coretronic Corporation
    Inventors: Wei-Min Chien, Yen-Ting Lin, Yao-Hung Chen
  • Publication number: 20260056568
    Abstract: A reference voltage supply circuit includes a first transistor, a second transistor, a first resistor, and a second resistor. The first transistor is coupled to a high voltage level terminal. The second transistor is coupled to a low voltage level terminal. The first resistor is coupled with the first transistor at a reference node for providing a reference voltage. The second resistor is coupled between the first resistor and the second transistor. The first resistor and the second resistor include variable resistors.
    Type: Application
    Filed: May 21, 2025
    Publication date: February 26, 2026
    Inventors: Wen-Hau Yang, Chun-Yu Luo, Yen-Ting Lin, Kuo-Chun Wu
  • Patent number: 12476540
    Abstract: A single-inductor multi-output (SIMO) DC-DC buck converter includes a first switch, a second switch, a third switch, a fourth switch, an inductor, an error amplifier circuit, an inductor current ripple emulator circuit, a comparison circuit, and a control circuit. The error amplifier circuit generates a first error signal and a second error signal according to the output voltages of the SIMO DC-DC buck converter. The inductor current ripple emulator circuit generates a sensed voltage according to a first terminal voltage and a second terminal voltage of the inductor. The comparison circuit generates a first comparison result and a second comparison result according to the first error signal, the second error signal, and the sensed voltage. The control circuit generates first to fourth control signals for respectively controlling the first to fourth switches according to the first comparison result and the second comparison result.
    Type: Grant
    Filed: March 20, 2024
    Date of Patent: November 18, 2025
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Wen-Hau Yang, Yen-Ting Lin, Chun-Yu Luo, Shih-Chieh Chen, Hung-Hsuan Cheng
  • Publication number: 20250224613
    Abstract: An adjustment method of a wearable display device includes steps of providing a display light beam to a light transmitting element to form an image, sensing an intensity of an ambient light to obtain a light intensity signal, and adjusting a brightness of the display light beam and/or a transmittance of the light transmitting element according to the light intensity signal. The adjustment method maintains good display effect of the wearable display device and improve user experience.
    Type: Application
    Filed: January 9, 2025
    Publication date: July 10, 2025
    Applicant: Coretronic Corporation
    Inventors: Yen-Ting Lin, Wei-Min Chien
  • Publication number: 20250210073
    Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.
    Type: Application
    Filed: March 17, 2025
    Publication date: June 26, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Qing Dong, Mahmut Sinangil, Yen-Ting Lin, Kerem Akarvardar, Carlos H. Diaz, Yih Wang
  • Patent number: 12272420
    Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Qing Dong, Mahmut Sinangil, Yen-Ting Lin, Kerem Akarvardar, Carlos H. Diaz, Yih Wang
  • Patent number: 12119052
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Publication number: 20240333155
    Abstract: A single-inductor multi-output (SIMO) DC-DC buck converter includes a first switch, a second switch, a third switch, a fourth switch, an inductor, an error amplifier circuit, an inductor current ripple emulator circuit, a comparison circuit, and a control circuit. The error amplifier circuit generates a first error signal and a second error signal according to the output voltages of the SIMO DC-DC buck converter. The inductor current ripple emulator circuit generates a sensed voltage according to a first terminal voltage and a second terminal voltage of the inductor. The comparison circuit generates a first comparison result and a second comparison result according to the first error signal, the second error signal, and the sensed voltage. The control circuit generates first to fourth control signals for respectively controlling the first to fourth switches according to the first comparison result and the second comparison result.
    Type: Application
    Filed: March 20, 2024
    Publication date: October 3, 2024
    Inventors: WEN-HAU YANG, YEN-TING LIN, CHUN-YU LUO, SHIH-CHIEH CHEN, HUNG-HSUAN CHENG
  • Publication number: 20240313625
    Abstract: A duty cycle control circuit generates a duty cycle control signal for controlling the duty cycle of a DC-DC buck conversion signal. The duty cycle control circuit includes: a dual ramp generator for generating a first ramp signal and a second ramp signal having the same frequency and different phases; a first comparator for comparing the first ramp signal with a feedback signal to generate a first control signal; a second comparator for comparing the second ramp signal with the feedback signal to generate a second control signal; and a logical circuit for performing a first predetermined logical operation according to the first control signal and a first conduction-control signal to generate a first part of the duty cycle control signal, and performing a second predetermined logical operation according to the second control signal and a second conduction-control signal to generate a second part of the duty cycle control signal.
    Type: Application
    Filed: March 11, 2024
    Publication date: September 19, 2024
    Inventors: WEN-HAU YANG, YEN-TING LIN, CHUN-YU LUO, WEI-WEN OU, HUNG-HSUAN CHENG
  • Publication number: 20240231203
    Abstract: A projection device includes a shell, a lens, two first ribs, two second ribs, and a sliding cover. The shell has a top plate, a left sidewall, and a right sidewall, the top plate is respectively connected to the left sidewall and the right sidewall, and the top plate has an opening. The lens is disposed in the shell and exposed by the opening. The two first ribs are disposed on the top plate, extending directions of the two first ribs are perpendicular to the left sidewall and the right sidewall, and the opening is disposed between the two first ribs. The sliding cover is slidably disposed on the shell for covering the opening. The two second ribs are disposed on a top cover body of the sliding cover, and one of the two second ribs is located between the two first ribs.
    Type: Application
    Filed: October 24, 2023
    Publication date: July 11, 2024
    Applicant: Coretronic Corporation
    Inventors: Wei-Min Chien, Yen-Ting Lin, Yao-Hung Chen
  • Publication number: 20240134256
    Abstract: A projection device includes a shell, a lens, two first ribs, two second ribs, and a sliding cover. The shell has a top plate, a left sidewall, and a right sidewall, the top plate is respectively connected to the left sidewall and the right sidewall, and the top plate has an opening. The lens is disposed in the shell and exposed by the opening. The two first ribs are disposed on the top plate, extending directions of the two first ribs are perpendicular to the left sidewall and the right sidewall, and the opening is disposed between the two first ribs. The sliding cover is slidably disposed on the shell for covering the opening. The two second ribs are disposed on a top cover body of the sliding cover, and one of the two second ribs is located between the two first ribs.
    Type: Application
    Filed: October 23, 2023
    Publication date: April 25, 2024
    Applicant: Coretronic Corporation
    Inventors: Wei-Min Chien, Yen-Ting Lin, Yao-Hung Chen
  • Publication number: 20240055048
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Publication number: 20230377614
    Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.
    Type: Application
    Filed: July 24, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Qing Dong, Mahmut Sinangil, Yen-Ting Lin, Kerem Akarvardar, Carlos H. Diaz, Yih Wang
  • Patent number: 11776867
    Abstract: A chip package including a heat-dissipating device, a first thermal interface material layer disposed on the heat-dissipating device, a patterned circuit layer disposed on the first thermal interface material layer, a chip disposed on the patterned circuit layer and electrically connected to the patterned circuit layer, and an insulating encapsulant covering the chip, the patterned circuit layer, and the first thermal interface material layer is provided. The first thermal interface material layer has a thickness between 100 ?m and 300 ?m. The first thermal interface material layer is located between the patterned circuit layer and the heat-dissipating device.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: October 3, 2023
    Assignee: Industrial Technology Research Institute
    Inventors: Kuo-Shu Kao, Tao-Chih Chang, Wen-Chih Chen, Tai-Jyun Yu, Po-Kai Chiu, Yen-Ting Lin, Wei-Kuo Han
  • Patent number: 11763882
    Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mahmut Sinangil, Yen-Huei Chen, Yen-Ting Lin, Hung-Jen Liao, Jonathan Tsung-Yung Chang
  • Patent number: 11735235
    Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.
    Type: Grant
    Filed: January 7, 2022
    Date of Patent: August 22, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Qing Dong, Mahmut Sinangil, Yen-Ting Lin, Kerem Akarvardar, Carlos H. Diaz, Yih Wang
  • Publication number: 20230174784
    Abstract: The present invention relates to a thermoplastic composition, a thermoplastic composite, and a method for producing the thermoplastic composite. In the method for producing the thermoplastic composite, a polymer, an acid-modified lignin with a specific element content and a compatibilizer with a specific melt flow index and a specific maleic anhydride content are used to produce the thermoplastic composite. Hydroxy groups of the acid-modified lignin react with maleic anhydride groups of the compatibilizer to generate ester bonds via an in-situ reaction catalyzed by acidic groups of the acid-modified lignin to enhance compatibility between the polymer and the lignin, thereby increasing a mechanical strength of the resulted thermoplastic composite.
    Type: Application
    Filed: November 29, 2022
    Publication date: June 8, 2023
    Inventors: Kwang-Ming CHEN, Jung-Hung KAO, Kun-Pei HSIEH, Chao-Shun CHANG, Yen-Ting LIN, Hung-Jue SUE
  • Patent number: D976852
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: January 31, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sheng-Tsai Wu, Hsin-Han Lin, Yuan-Yin Lo, Kuo-Shu Kao, Tai-Jyun Yu, Han-Lin Wu, Yen-Ting Lin