Patents by Inventor Yi An SHIH

Yi An SHIH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210143861
    Abstract: A transceiver device includes a digital baseband circuit, a first circuit portion, and a second circuit portion. The digital baseband circuit is configured to analyze power of an input signal, in order to generate a first control signal and a second control signal. The first circuit portion has a first gain, and is configured to be selected according to the first control signal to process the input signal to generate output signals. The second circuit portion has a second gain higher than the first gain, and is configured to be selected according to the second control signal to process the input signal to generate the output signals. The first circuit portion includes an N-way filter circuit, and the N-way filter circuit is configured to modulate the input signal according to first oscillating signals to perform a filtering operation.
    Type: Application
    Filed: October 27, 2020
    Publication date: May 13, 2021
    Inventors: Chia-Yi Lee, Kuan-Yu Shih, Ka-Un Chan
  • Publication number: 20210139749
    Abstract: The present invention provides a polymer composition for pressure sensitive adhesives or films thereof. The polymer composition comprises 20-40 parts by weight of a tackifier; and 60-80 parts by weight of a polymer, wherein the polymer and the tackifier are 100 parts by weight. The polymer comprises at least a first vinyl aromatic based copolymer formed by polymerization of vinyl aromatic monomer and conjugated diene monomer, wherein a vinyl aromatic monomer content of the first vinyl aromatic based copolymer is 16 wt %˜28 wt %, a vinyl structure content of a conjugated diene monomer content in the first vinyl aromatic based copolymer is 32 wt %˜50 wt %; and a melt flow index (MFI) of the first vinyl aromatic based copolymer is 20 g/10 min˜60 g/10 min (230° C., 2.16 kg). The present invention also provides the pressure sensitive adhesives or films made from the polymer composition.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 13, 2021
    Inventors: Hsi-Hsin Shih, Wen-Pin Tsai, Feng-Yu Yang, Tai-Yi Shiu, Ching Ting
  • Patent number: 11005030
    Abstract: A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor.
    Type: Grant
    Filed: March 10, 2019
    Date of Patent: May 11, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, Chen-Yi Weng, Chin-Yang Hsieh, I-Ming Tseng, Jing-Yin Jhang, Yu-Ping Wang
  • Publication number: 20210136624
    Abstract: A wireless communication device is disclosed. The wireless communication device includes a processor, a transceiver coupled to the processor, and a memory coupled to the processor. The memory is configured to store a plurality of instructions and the plurality of instructions are executed by the processor to perform operations of storing, in the memory, a duplication of each of the plurality of packets transmitted by a streaming provider; and in response to a request of retransmission transmitted by a terminal device for a lost packet, determining whether the duplication of the lost packet is stored in the memory.
    Type: Application
    Filed: June 23, 2020
    Publication date: May 6, 2021
    Inventors: Ping-Ke Shih, Chin-Yi Lin, Yi-Shou Hsu
  • Patent number: 10991649
    Abstract: A semiconductor device includes a first substrate, a pad array, a conductive bump, a first via and a dielectric. The pad array, formed on a surface of the first substrate, includes a first type pad and a second type pad at a same level. The conductive bump connects one of the first type pad of the second type pad to a second substrate. The first via, connected to a conductive feature at a different level to the first type pad, is located within a projection area of the first type pad and directly contacts the first type pad. The second type pad is laterally connected with a conductive trace on the same level. The conductive trace is connected to a second via at a same level with the first via. The dielectric in the first substrate contacts the second type pad. The second type pad is floated on the dielectric.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsung-Yuan Yu, Hao-Yi Tsai, Chao-Wen Shih, Hung-Yi Kuo, Pi-Lan Chang
  • Publication number: 20210111334
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Application
    Filed: December 23, 2020
    Publication date: April 15, 2021
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, JUN XIE
  • Publication number: 20210068278
    Abstract: A protection device including a first housing, a second housing, a power component, a protective cover and a circuit board is provided. The second housing and the first housing are assembled to each other to define an internal space. The power component is disposed on the second housing and located in the internal space. The protective cover covers the power component and is located in the internal space. The circuit board is disposed in the internal space, and the protective cover is located between the circuit board and the power component. At least one pin of the power component protrudes beyond the circuit board through the protective cover and the circuit board.
    Type: Application
    Filed: October 14, 2019
    Publication date: March 4, 2021
    Applicants: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, Lite-On Technology Corporation
    Inventors: Yi-An Shih, Wei-Hung Hsu, Yuan-Syun Luo, Wei-Yu Hsu, Chia-Cheng Huang
  • Publication number: 20210035620
    Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
    Type: Application
    Filed: August 29, 2019
    Publication date: February 4, 2021
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
  • Patent number: 10910553
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: February 2, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
  • Publication number: 20210020691
    Abstract: A magnetoresistive random access memory (MRAM), including multiple cell array regions, multiple MRAM cells disposed in the cell array region, a silicon nitride liner conformally covering on the MRAM cells, an atomic layer deposition dielectric layer covering on the silicon nitride liner in the cell array region, wherein the surface of atomic layer deposition dielectric layer is a curved surface concave downward to the silicon nitride liner at the boundary of MRAM cells, and an ultra low-k dielectric layer covering on the atomic layer deposition dielectric layer.
    Type: Application
    Filed: August 6, 2019
    Publication date: January 21, 2021
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Ying-Cheng Liu, Yi-Hui Lee, Chin-Yang Hsieh, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20210020828
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, and a top electrode layer on the magnetic tunnel junction stack, wherein the material of top electrode layer is titanium nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Application
    Filed: August 5, 2019
    Publication date: January 21, 2021
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, JUN XIE
  • Publication number: 20200373478
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.
    Type: Application
    Filed: June 12, 2019
    Publication date: November 26, 2020
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20200266335
    Abstract: A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor.
    Type: Application
    Filed: March 10, 2019
    Publication date: August 20, 2020
    Inventors: Hui-Lin Wang, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, Chen-Yi Weng, Chin-Yang Hsieh, I-Ming Tseng, Jing-Yin Jhang, Yu-Ping Wang
  • Patent number: 10727397
    Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: July 28, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yi-Wei Tseng, Meng-Jun Wang, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang, Yu-Ping Wang, Chien-Ting Lin, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, I-Ming Tseng
  • Publication number: 20200227473
    Abstract: An MRAM structure includes a dielectric layer. A contact hole is disposed in the dielectric layer. A contact plug fills in the contact hole and protrudes out of the dielectric layer. The contact plug includes a lower portion and an upper portion. The lower portion fills in the contact hole. The upper portion is outside of the contact hole. The upper portion has a top side and a bottom side greater than the top side. The top side and the bottom side are parallel. The bottom side is closer to the contact hole than the top side. An MRAM is disposed on the contact hole and contacts the contact plug.
    Type: Application
    Filed: February 19, 2019
    Publication date: July 16, 2020
    Inventors: Yi-Hui Lee, I-Ming Tseng, Ying-Cheng Liu, Yi-An Shih, Yu-Ping Wang
  • Publication number: 20200227625
    Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.
    Type: Application
    Filed: January 29, 2019
    Publication date: July 16, 2020
    Inventors: Hui-Lin Wang, Yi-Wei Tseng, Meng-Jun Wang, Chen-Yi Weng, Chin-Yang Hsieh, Jing-Yin Jhang, Yu-Ping Wang, Chien-Ting Lin, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, I-Ming Tseng
  • Patent number: 10712795
    Abstract: Systems and methods are provided for controlling two or more PSUs of a server system. An exemplary method comprises first determining whether the PSUs are switched on to an AC power source. If the PSUs are found not switched on to an AC power source, the method further comprises restarting the AC power source for the PSUs and completing a software-based recovery process. If the PSUs are found to be switched on to an AC power source, the method further comprises determining whether the PSUs meet a predefined criterion. If the PSUs do meet a predefined criterion, the method further comprises disabling a cold-redundancy mode for the PSUs. If the PSUs do not meet a predefined criterion, the method further comprises starting a wake-up process for a first PSU from a cold-redundancy mode.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 14, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Yi-Chieh Chen, Yueh-Chang Wu, Ching-Yi Shih
  • Patent number: 10699939
    Abstract: Semiconductor structure and fabrication method are provided. The method includes: providing a substrate including device regions and isolation regions, adjacent with one another; providing discrete fins on the substrate, pitches between adjacent fins being substantially same; forming a protective layer on the sidewalls of the fins; removing a partial thickness of the fins in the isolation regions along with a partial thickness of the protective layer in the isolation regions by a first etching process; forming dummy fins by a second etching process to etch the remaining fins in the isolation regions using the remaining protective layers as a mask; removing the remaining protective layer after the second etching process; and forming isolation structures in the isolation regions on the substrate. The isolation structures have a top lower than the fins in the device regions and higher than the dummy fins in the isolation regions.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 30, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Hua Yong Hu, Yi Shih Lin
  • Patent number: 10693490
    Abstract: A Sigma-Delta (?-?) analog-to-digital converter (ADC) and operation method thereof are provided. The ?-? ADC includes a ?-? modulator, a dynamic element matching (DEM) circuit and a control circuit. An input terminal of the ?-? modulator is configured to receive an analog signal. The ?-? modulator is configured to convert the analog signal into a digital signal based on a feedback signal. The DEM circuit is coupled to the ?-? modulator to receive the digital signal. The DEM circuit is configured to perform a DEM algorithm on the digital signal to generate a feedback signal, and provide the feedback signal to the ?-? modulator. The control circuit listens to the digital signal to detect a mute period. The control circuit disables the DEM circuit during the mute period to suspend a progress of the DEM algorithm.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: June 23, 2020
    Assignee: Faraday Technology Corp.
    Inventors: Chiao-Min Chen, Min-Yuan Wu, Shih-Yi Shih, Po-Liang Chen
  • Patent number: 10691569
    Abstract: A system for testing a data storage device includes the data storage device, an electronic device and a computer device. The electronic device includes a host device coupled to the data storage device and communicating with the data storage device via an interface logic. The computer device is coupled to the electronic device and is configured to issue a plurality of commands to test the data storage device in a test procedure. When the electronic device has been successfully started up, the computer device issues a first command to the electronic device to trigger the electronic device to enter a hibernate mode. After waiting for a first predetermined period of time, the computer device issues a second command to the electronic device, so as to wake up the electronic device.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: June 23, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Po-Yi Shih