Patents by Inventor YI-AN WU

YI-AN WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11976123
    Abstract: Disclosed herein are agnostic anti-CD40 antibodies and methods of using such for eliciting CD40 signaling, thereby enhancing immune responses, such as dendritic cell functions. The antibodies disclosed herein may be used to treat diseases, such as cancer and immune disorders.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: May 7, 2024
    Assignee: LYVGEN BIOPHARMA HOLDINGS LIMITED
    Inventors: Jieyi Wang, Yi Wu
  • Patent number: 11978664
    Abstract: A method includes forming a first conductive feature over a semiconductor substrate, forming an ILD layer over the first conductive feature, patterning the ILD layer to form a trench, and forming a conductive layer over the patterned ILD layer to fill the trench. The method further includes polishing the conductive layer to form a via contact configured to interconnect the first conductive feature with a second conductive feature, where polishing the conductive layer exposes a top surface of the ILD layer, polishing the exposed top surface of the ILD layer, such that a top portion of the via contact protrudes from the exposed top surface of the ILD layer, and forming the second conductive feature over the via contact, such that the top portion of the via contact extends into the second conductive feature.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pang-Sheng Chang, Chao-Hsun Wang, Kuo-Yi Chao, Fu-Kai Yang, Mei-Yun Wang, Li-Chieh Wu, Chun-Wei Hsu
  • Publication number: 20240142492
    Abstract: The present invention relates to a pogo pin cooling system and a pogo pin cooling method and an electronic device testing apparatus having the system. The system mainly comprises a coolant circulation module, which includes a coolant supply channel communicated with an inlet of a chip socket and a coolant recovery channel communicated with an outlet of the chip socket. When an electronic device is accommodated in the chip socket, the coolant circulation module supplies a coolant into the chip socket through the coolant supply channel and the inlet, and the coolant passes through the pogo pins and then flows into the coolant recovery channel through the outlet.
    Type: Application
    Filed: October 28, 2022
    Publication date: May 2, 2024
    Inventors: I-Shih TSENG, Xin-Yi WU, I-Ching TSAI, Chin-Yi OUYANG
  • Publication number: 20240144372
    Abstract: In various examples, interactive systems that use neural networks to determine financial investment predictions or recommendations are presented. Systems and methods are disclosed that determine financial predictions or recommendations associated with one or more investments using a neural network(s). The financial predictions may include a predicted movement of an investment (e.g., extremely down, down, preserved, up, extremely up, etc.), a predicted price of an investment (e.g., a future stock price, etc.), a specific investment for a user to buy/sell/trade, and/or so forth. In some examples, the systems and methods may include an interactive system(s), such as a dialogue system(s), that interacts with users to provide the financial predictions.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 2, 2024
    Inventors: Xianchao Wu, Yi Dong, Scott Nunweiler
  • Publication number: 20240145421
    Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.
    Type: Application
    Filed: October 27, 2023
    Publication date: May 2, 2024
    Inventors: Kuan-Neng CHEN, Zhong-Jie HONG, Chih-I CHO, Ming-Wei WENG, Chih-Han CHEN, Chiao-Yen WANG, Ying-Chan HUNG, Hong-Yi WU, CHENG-YEN HSIEH
  • Publication number: 20240145715
    Abstract: A battery positive electrode material including lithium ferromanganese phosphate particles and active particles dispersed in voids between the lithium ferromanganese phosphate particles. The active particles include one or more of lithium nickel cobalt manganate particles, lithium nickel cobalt aluminate particles, lithium-rich manganese-based material particles, lithium cobaltate particles, spinel lithium manganate LiMn2O4 particles and layered lithium manganate LiMnO2 particles. The ratio of the median particle diameter of lithium ferromanganese phosphate to that of the active particles is between 3 and 8. In the battery positive electrode material, the content of percentage by weight of the lithium ferromanganese phosphate is between 70% and 90%, and the content of percentage by weight of the active particles is between 10% and 30%.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: Bin CHENG, Yi PAN, Minghao ZHUANG, Ruoyi DENG, Pengyu WU
  • Publication number: 20240144467
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Publication number: 20240144373
    Abstract: In various examples, interactive systems that use neural networks to determine financial investment predictions or recommendations are presented. Systems and methods are disclosed that determine financial predictions or recommendations associated with one or more investments using a neural network(s). The financial predictions may include a predicted movement of an investment (e.g., extremely down, down, preserved, up, extremely up, etc.), a predicted price of an investment (e.g., a future stock price, etc.), a specific investment for a user to buy/sell/trade, and/or so forth. In some examples, the systems and methods may include an interactive system(s), such as a dialogue system(s), that interacts with users to provide the financial predictions.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 2, 2024
    Inventors: Xianchao Wu, Yi Dong, Scott Nunweiler
  • Publication number: 20240141716
    Abstract: The door sill includes a sill deck and a rail carrier assembly having a function of height adjustment. The rail carrier assembly is configured on the sill deck. The rail carrier assembly includes a rail cap, a rail carrier, an adjustment nut and an adjustment screw. The rail cap is snapped onto an upper end of the rail carrier. A groove is formed in the sill deck for the rail carrier to fit in. A nut installation hole is formed in the rail carrier. The adjustment nut is assembled at the nut installation hole, and is in threaded fit with the adjustment screw. The adjustment screw drives the adjustment nut to move up or down in an axial direction of the adjustment screw through rotation, thereby altering the height of the rail carrier fitted in the groove and altering the height of the rail cap.
    Type: Application
    Filed: December 26, 2022
    Publication date: May 2, 2024
    Inventors: Minghui CHEN, Yi CAO, James William Meeks, Xuhui WU
  • Publication number: 20240139581
    Abstract: An electric treadmill includes a treadmill frame, an endless belt, a motor coupled to the endless belt for driving the endless belt to rotate, a brake device and a lifting device. The brake device has a rotating disc coaxially fixed to a motor shaft of the motor and a magnetic brake mechanism. The magnetic brake mechanism has at least one magnetic portion for applying a drag force against rotation of the rotating disc. The lifting device is operable to drive the magnetic brake mechanism to move between a first position where the magnetic portion is located close to the rotating disc and a second position where the magnetic portion is located away from the rotating disc. When there is no electric power supplied to the electric treadmill, the magnetic brake mechanism will automatically move to the first position due to gravity to stop rotation of the endless belt.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 2, 2024
    Inventors: Yung-Fa Wang, Mei-Yi Wu
  • Publication number: 20240145919
    Abstract: An antenna module includes a first metal plate and a frame body. The frame body surrounds the first metal plate. The frame body includes a first antenna radiator, a second antenna radiator, a third antenna radiator, a first breakpoint and a second breakpoint. The first antenna radiator includes a first feeding end and excites a first frequency band. The second antenna radiator includes a second feeding end and excites a second frequency band. The third antenna radiator includes a third feeding end and excites a third frequency band. The first breakpoint is located between the first antenna radiator and the second antenna radiator. The second breakpoint is located between the second antenna radiator and the third antenna radiator. An electronic device including the above-mentioned antenna module is also provided.
    Type: Application
    Filed: September 6, 2023
    Publication date: May 2, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Shih-Keng Huang, Chao-Hsu Wu, Chih-Wei Liao, Sheng-Chin Hsu, Hao-Hsiang Yang, Tse-Hsuan Wang
  • Publication number: 20240145898
    Abstract: An electronic device including a metal casing and at least one antenna module is provided. The metal casing includes at least one window. The at least one antenna module is disposed in the at least one window. The at least one antenna module includes a first radiator and a second radiator. The first radiator includes a feeding end, a first ground end joined to the metal casing, a second ground end, a first portion extending from the feeding end to the first ground end, and a second portion extending from the feeding end to the second ground end. A first coupling gap is between the second radiator and the first portion. A second coupling gap is between at least part of the second radiator and the metal casing, and the second radiator includes a third ground end joined to the metal casing.
    Type: Application
    Filed: September 8, 2023
    Publication date: May 2, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Sheng-Chin Hsu, Chih-Wei Liao, Hau Yuen Tan, Cheng-Hsiung Wu, Shih-Keng Huang
  • Patent number: 11973163
    Abstract: A light emitting device includes an epitaxial structure and first and second electrodes on a side of the epitaxial structure. The epitaxial structure includes a first-type semiconductor layer, an active layer, and a second-type semiconductor layer. The active layer is disposed between the first-type semiconductor layer and the second-type semiconductor layer. The first electrode is disposed on the epitaxial structure to be electrically connected with the first-type semiconductor layer. The second electrode is disposed on the epitaxial structure to be electrically connected with the second-type semiconductor layer. The second electrode is in ohmic contact with a second-type window sublayer of the second-type semiconductor layer.
    Type: Grant
    Filed: January 20, 2023
    Date of Patent: April 30, 2024
    Assignee: Tianjin Sanan Optoelectronics Co., Ltd.
    Inventors: ChingYuan Tsai, Chun-Yi Wu, Fulong Li, Duxiang Wang, Chaoyu Wu, Wenhao Gao, Xiaofeng Liu, Weihuan Li, Liming Shu, Chao Liu
  • Patent number: 11974510
    Abstract: The present disclosure provides a memory structure, including a first interlayer dielectric layer (ILD), a second ILD over the first ILD, wherein at least a portion of an interconnect structure is in the second ILD, a first switch between the first ILD and the second ILD, a second switch over the first switch, and a first phase change material stacking with the first switch and the second switch.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: April 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Jau-Yi Wu
  • Patent number: 11974482
    Abstract: A display substrate and related devices are provided. The display substrate includes a plurality of first sub-pixels, second sub-pixels and third sub-pixels. In a first direction, the first sub-pixels and the third sub-pixels are arranged alternately to form a plurality of first sub-pixel rows, the second sub-pixels form a plurality of second sub-pixel rows, the first sub-pixel rows and the second sub-pixel rows are arranged alternately in a second direction, connection lines of center points of two first sub-pixels and two third sub-pixels form a first virtual quadrilateral, the two first sub-pixels are located at two vertex angles of the first virtual quadrilateral which are opposite to each other, one second sub-pixel is located within the first virtual quadrilateral, and the first virtual quadrilateral includes two interior angles each being equal to 90° and two interior angles each being not equal to 90°.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: April 30, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qian Xu, Tong Niu, Yan Huang, Guomeng Zhang, Chang Luo, Jianpeng Wu, Peng Xu, Fengli Ji, Yi Zhang, Benlian Wang, Ming Hu
  • Patent number: 11969264
    Abstract: An adaptive controller used in a photoplethysmography sensing system, comprises a plurality of hardware circuits which are configured to: receive a photoplethysmography signal (hereinafter, “PPG signal”) processed; determine whether the PPG signal processed satisfies with a requirement; output the PPG signal processed if the PPG signal processed satisfies with a requirement; and adjust a gain of an amplifier for amplifying the PPG signal and/or a driving signal of a light source if the PPG signal processed does not satisfy with a requirement.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: April 30, 2024
    Assignee: Amengine Corporation
    Inventors: Paul C. P. Chao, Tse-Yi Tu, Bo-Wei Pan, Yan-Hwa Wu
  • Publication number: 20240136299
    Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Wei-Yu Chen, Chun-Chih Chuang, Kuan-Lin Ho, Yu-Min Liang, Jiun Yi Wu
  • Publication number: 20240135883
    Abstract: A pixel driving circuit, a display panel and a driving method of the pixel driving circuit are provided by the present disclosure. The pixel driving circuit includes a driving transistor, a reset module, a writing module, a first control module, and a light emitting device. The pixel driving circuit with the 5T2C structure can compensate the threshold voltage drift of the driving transistor, improve the luminous uniformity of the light emitting device, and further improve the image quality.
    Type: Application
    Filed: December 28, 2022
    Publication date: April 25, 2024
    Applicant: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Yi WU, Shijian BAO
  • Publication number: 20240136441
    Abstract: A semiconductor device includes a substrate, and a first transistor disposed on the substrate. The first transistor includes a first channel layer, a magnesium oxide layer, a first gate electrode, a first gate dielectric and first source/drain electrodes. A crystal orientation of the first channel layer is <100> or <110>. The magnesium oxide layer is located below the first channel layer and in contact with the first channel layer. The first gate electrode is located over the first channel layer. The first gate dielectric is located in between the first channel layer and the first gate electrode. The first source/drain electrodes are disposed on the first channel layer.
    Type: Application
    Filed: February 5, 2023
    Publication date: April 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ken-Ichi Goto, Cheng-Yi Wu
  • Patent number: D1026191
    Type: Grant
    Filed: December 26, 2022
    Date of Patent: May 7, 2024
    Inventors: Luyao Han, Yi Liu, Ziqing Ruan, Yanda Li, Huanlong Wu, Linjun Yu