Abstract: A device including a first vertical field effect transistor having a first drain/source region and a second drain/source region, and a second vertical field effect transistor having a third drain/source region and a fourth drain/source region. The device including a first power contact situated on a frontside of the device and coupled to the first drain/source region, a second power contact situated on the frontside of the device and coupled to the third drain/source region, and a contact situated on a backside of the device and coupled to the second drain/source region and to the fourth drain/source region.

Abstract: A method of slicing wafers from a monocrystalline semiconductor ingot includes attaching a circumferential edge of the ingot to a bond beam and positioning sacrificial disks adjacent longitudinal end faces of the ingot. One sacrificial disk is positioned adjacent each of the longitudinal end faces. The method also includes connecting the bond beam to a wire saw that includes a wire web and performing a slicing operation on the ingot by operating the wire saw to drive the wire web and move the bond beam and the ingot in a movement direction towards the wire web to slice the wafers from the ingot.

Abstract: A system for slicing wafers from a monocrystalline semiconductor ingot includes a wire saw, a bond beam, the monocrystalline semiconductor ingot, and two sacrificial disks. The wire saw includes a wire web and wire guides operable to drive the wire web during a slicing operation. The bond beam is connected to the wire saw. The wire saw is operable to move the bond beam in a movement direction towards the wire web during the slicing operation to slice the wafers from the ingot. The ingot includes longitudinal end faces and a circumferential edge extending between the longitudinal end faces. The ingot is attached to the bond beam along the circumferential edge. One sacrificial disk is positioned adjacent each of the longitudinal end faces of the ingot to inhibit uncontrolled breakage of the wafers during the slicing operation.

Abstract: A resin compound has a structure represented by a chemical formula (I): In the chemical formula (I), each R1 independently represents a C1-C20 alkylene group or a C7-C40 alkylarylene group, and R1 are the same or different from each other; n independently represents an integer of 1-4; each R2 independently represents a C1-C20 alkyl group or a C2-C20 terminal alkenyl group, and R2 are the same or different from each other. When at least one of R1 represents a C1-C20 alkylene group, at least one of R2 is a C2-C20 terminal alkenyl group.

Abstract: A connector includes a circuit board, signal wires, and a ground bar. The circuit board has an upper surface and a lower surface opposite to each other. The upper surface includes upper signal contacts and upper ground contacts. The lower surface includes lower signal contacts and lower ground contacts. Some of the signal wires are in contact with the upper signal contacts respectively. Others of the signal wires are in contact with the lower signal contacts respectively. The ground bar is in contact with the upper ground contacts and the lower ground contacts.

Abstract: Semiconductor devices and methods of fabrication are provided. A method includes providing a semiconductor structure with a first sidewall distanced from a second sidewall, fins located between the first sidewall and the second sidewall, and isolation regions located between the first sidewall and the second sidewall, wherein adjacent fins are separated by a respective isolation region. The method further includes performing a plasma etching process to etch the fins and the isolation regions, wherein the plasma etching process chemically etches the fins, wherein the plasma etching process physically etches the isolation regions to recesses defining a crown-shaped depth profile.

Abstract: A method of manufacturing a resistor-transistor-logic circuit with GaN structures, including steps of forming a GaN layer, an AlGaN barrier layer and a p-type doped GaN capping layer on a substrate, patterning the p-type doped GaN capping layer into multiple p-type doped GaN capping patterns, wherein the GaN layer under parts of the p-type doped GaN capping patterns is converted into gate depletion regions, and the GaN layer not covered by the p-type doped GaN capping patterns in a resistor region functions as 2DEG resistors, forming a passivation layer on the GaN layer and the p-type doped GaN capping patterns, forming multiple sources and drains on the GaN layer, and forming multiple gates on the p-type doped GaN capping patterns, wherein the gates, sources and drains in a high-voltage device region constitute high-voltage HEMTs, and the gates, sources and drains in a low-voltage device region constitute low-voltage logic FETs.

Abstract: A solution that allows the avatar corresponding to the target object tracked by the external tracking device can be properly displayed in the visual content that corresponds to the field of view of the virtual camera, even if the coordinate systems used by the host and the external tracking device are different.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.

Abstract: A resistor-transistor-logic circuit with GaN structures, including a 2DEG resistor having a drain connected with an operating voltage, and a logic FET having a gate connected to an input voltage, a source grounded and a drain connected with a source of the 2DEG resistor and connected collectively to an output voltage.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: A resistor with GaN structures, including a GaN layer with a 2DEG resistor region and an undoped polysilicon resistor region, an AlGaN barrier layer on the GaN layer in the 2DEG resistor region, multiple p-type doped GaN capping layers arranged on the AlGaN barrier layer so that the GaN layer not covered by the p-type doped GaN capping layers in the 2DEG resistor region is converted into a 2DEG resistor, a passivation layer on the GaN layer, and an undoped polysilicon layer on the passivation layer in the undoped polysilicon resistor region and functions as an undoped polysilicon resistor.

Abstract: An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.

Abstract: A semiconductor device includes a semiconductor substrate; an isolation region disposed on the semiconductor substrate; a plurality of dummy fins disposed over the isolation region and partially extending into the isolation region; and a dielectric material disposed between the plurality of dummy fins, and partially extending through the isolation region and partially into the semiconductor substrate.

Abstract: A method includes forming a gate stack on a semiconductor region, wherein the semiconductor region is over a bulk semiconductor substrate. The gate stack is etched to form a first trench, wherein a plurality of protruding semiconductor fins are revealed to the first trench. The plurality of protruding semiconductor fins are etched to form a plurality of second trenches extending into the bulk semiconductor substrate. The plurality of second trenches are underlying and joined to the first trench. The plurality of second trenches include a first outmost trench having a first depth, a second outmost trench, and an inner trench between the first outmost trench and the second outmost trench. The inner trench has a second depth equal to or smaller than the first depth. A fin isolation region is formed to fill the first trench and the plurality of second trenches.

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.

Abstract: An encoded substrate to be filmed by a camera device for generating an image is provided. The encoded substrate includes a plurality of grids arranged in a form of two-dimensional array, wherein each grid includes a first pattern and a second pattern not overlapped with each other. The first pattern corresponds to a first-dimensional encoded value, and the second pattern corresponds to a second-dimensional encoded value. The image is processed by a processor for scanning the plurality of grids. In a first-dimensional direction, the processor outputs a first coordinate according to at least two first patterns corresponding to at least two consecutive grids among the plurality of grids. In a second-dimensional direction, the processor outputs a second coordinate according to at least two second patterns corresponding to at least two consecutive grids among the plurality of grids.

Abstract: A semiconductor device includes a substrate; a first fin structure extending along a first lateral direction; a second fin structure extending along the first lateral direction; a first gate structure extending along a second lateral direction and straddles the first fin structure; a second gate structure extending along the second lateral direction and straddles the second fin structure. The semiconductor device further includes a dielectric cut structure that separates the first and second gate structures from each other. The dielectric cut structure extends into the substrate and comprises a first portion and a second portion. A width of the first portion along the second lateral direction increases with increasing depth into the substrate and a width of the second portion along the second lateral direction decreases with increasing depth into the substrate. The second portion is located below the first portion.