Abstract: Techniques are disclosed relating to improving memory reliability. In some embodiments, memory circuitry includes memory cells configured to store data, interface circuitry, and on-die error correcting code (ECC) circuitry. The ECC circuitry may check read data from the memory cells for errors and correct detected correctable errors to generate corrected data. The memory circuitry may provide read data to a requesting circuit via the interface circuitry, including one or more sets of corrected data from the on-die ECC circuitry. The memory circuitry may provide a decoding status flag (DSF) via the interface circuitry, including to: set the DSF to a first value in response to no error being detected for a given set of provided read data, set the DSF to a second value in response to a correctable error that was detected and corrected by the on-die ECC circuitry to provide a given set of read data, and set the DSF to a third value in response to an uncorrectable error detected by the on-die ECC circuitry.

Abstract: A MRAM layout structure with multiple unit cells, including a first word line, a second word line and a third word line extending through active areas, wherein two ends of a first MTJ are connected respectively to a second active area and one end of a second MTJ, and two ends of a third MTJ are connected respectively to a third active area and one end of a fourth MTJ, and a first bit line and a second bit line connected respectively to the other end of the second MTJ and the other end of the fourth MTJ.

Abstract: A resin composition includes 100 parts by weight of hydrocarbon resin polymers and 0.01 to 50 parts by weight of divinyl aromatic compound. A substrate structure includes a resin layer and a conductive layer disposed on the resin layer, wherein the resin layer is formed from the resin composition. A manufacturing method of the resin composition includes the following steps: providing a mixture, wherein the mixture includes a monovinyl aromatic compound and a divinyl aromatic compound, and optionally includes a bridged ring compound; polymerizing the mixture to form a crude composition; and purifying the crude composition to prepare the resin composition.

Abstract: A micro light emitting device display apparatus including a substrate, a plurality of micro light emitting devices, an isolation layer, and at least one first air gap is provided. The substrate has a plurality of connection pads. The micro light emitting devices are discretely disposed on the substrate. The isolation layer is disposed between the substrate and each of the micro light emitting devices. The at least one first air gap is disposed between the substrate and a surface of the isolation layer facing the substrate.

Abstract: A display panel includes a substrate, first, second, and third data lines, scan lines, a first active device, a second active device, and pixel electrodes. The first and the third data lines have a first polarity. The second data line has a second polarity. The first polarity is different from the second polarity. A source electrode of the first active device disposed between the first data line and the second data line is electrically connected to the first data line. An extension region of the semiconductor pattern of the first active device extends toward and overlaps the second data line. A source electrode of the second active device disposed between the second data line and the third data line is electrically connected to the second data line. An extension region of the semiconductor pattern of the second active device extends toward and overlaps the third data line.

Abstract: The present disclosure provides a semiconductor light-emitting device and a semiconductor light-emitting component. The semiconductor light-emitting device includes a substrate, a first semiconductor contact layer, a semiconductor light-emitting stack including an active layer, a first-conductivity-type contact structure, a second semiconductor contact layer, a second-conductivity-type contact structure and a first electrode pad. The first-conductivity-type contact structure is electrically connected to the first semiconductor contact layer. The second-conductivity-type contact structure is electrically connected to the second semiconductor contact layer. The first-conductivity-type contact structure has a first bottom surface and a first top surface, and the active layer has a second bottom surface and a second top surface.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, an active region on the substrate, and a gate structure, a source conductor, and a drain conductor disposed on the active region. The semiconductor device further comprises a first type doped region of the active region below the gate structure and a second type doped region of the active region adjacent to the first type doped region, and the first type doped region is different from the second type doped region. The second type doped region is configured to function as a resistor.

Abstract: Some implementations described herein include operating components in a lithography system at variable speeds to reduce, minimize, and/or prevent particle generation due to rubbing of or collision between contact parts of the components. In some implementations, a component in a path of transfer of a semiconductor substrate in the lithography system is operated at a relatively high movement speed through a first portion of an actuation operation, and is operated at a reduced movement speed (e.g., a movement speed that is less than the high movement speed) through a second portion of the actuation operation in which contact parts of the component are to interact. The reduced movement speed reduces the likelihood of particle generation and/or release from the contact parts when the contact parts interact, while the high movement speed provides a high semiconductor substrate throughput in the lithography system.

Abstract: A coil module is provided, including a second coil mechanism. The second coil mechanism includes a third coil assembly and a second base corresponding to the third coil assembly. The second base has a positioning assembly corresponding to a first coil mechanism.

Abstract: Systems and methods as described herein may take a variety of forms. In one example, systems and methods are provided for a circuit for powering a voltage regulator. A voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. A power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.

Abstract: An organic electroluminescent material is used for a sensitizer layer of an organic light-emitting diode. The organic electroluminescent material includes a structure of the following General Formula (1): A is selected from the group consisting of General Formula (2), a carbazole group, and a substituted benzimidazole group. The present invention also discloses an organic light-emitting diode which has a sensitizer layer. The sensitizer layer includes a structure of General Formula (1).

Abstract: Hydrofluoric acid waste streams from semiconductor device manufacturing processes are collected and converted to cryolite utilizing disclosed systems and processes. The systems and processes are able to utilize hydrofluoric acid waste streams from multiple different sources. The systems and processes utilizing control delivery of reactant so that the produced cyrolite has low impurity levels and meets industry standards.

Abstract: A device including a first vertical field effect transistor having a first drain/source region and a second drain/source region, and a second vertical field effect transistor having a third drain/source region and a fourth drain/source region. The device including a first power contact situated on a frontside of the device and coupled to the first drain/source region, a second power contact situated on the frontside of the device and coupled to the third drain/source region, and a contact situated on a backside of the device and coupled to the second drain/source region and to the fourth drain/source region.

Abstract: A method of slicing wafers from a monocrystalline semiconductor ingot includes attaching a circumferential edge of the ingot to a bond beam and positioning sacrificial disks adjacent longitudinal end faces of the ingot. One sacrificial disk is positioned adjacent each of the longitudinal end faces. The method also includes connecting the bond beam to a wire saw that includes a wire web and performing a slicing operation on the ingot by operating the wire saw to drive the wire web and move the bond beam and the ingot in a movement direction towards the wire web to slice the wafers from the ingot.

Abstract: A system for slicing wafers from a monocrystalline semiconductor ingot includes a wire saw, a bond beam, the monocrystalline semiconductor ingot, and two sacrificial disks. The wire saw includes a wire web and wire guides operable to drive the wire web during a slicing operation. The bond beam is connected to the wire saw. The wire saw is operable to move the bond beam in a movement direction towards the wire web during the slicing operation to slice the wafers from the ingot. The ingot includes longitudinal end faces and a circumferential edge extending between the longitudinal end faces. The ingot is attached to the bond beam along the circumferential edge. One sacrificial disk is positioned adjacent each of the longitudinal end faces of the ingot to inhibit uncontrolled breakage of the wafers during the slicing operation.

Abstract: A resin compound has a structure represented by a chemical formula (I): In the chemical formula (I), each R1 independently represents a C1-C20 alkylene group or a C7-C40 alkylarylene group, and R1 are the same or different from each other; n independently represents an integer of 1-4; each R2 independently represents a C1-C20 alkyl group or a C2-C20 terminal alkenyl group, and R2 are the same or different from each other. When at least one of R1 represents a C1-C20 alkylene group, at least one of R2 is a C2-C20 terminal alkenyl group.

Abstract: A connector includes a circuit board, signal wires, and a ground bar. The circuit board has an upper surface and a lower surface opposite to each other. The upper surface includes upper signal contacts and upper ground contacts. The lower surface includes lower signal contacts and lower ground contacts. Some of the signal wires are in contact with the upper signal contacts respectively. Others of the signal wires are in contact with the lower signal contacts respectively. The ground bar is in contact with the upper ground contacts and the lower ground contacts.

Abstract: Semiconductor devices and methods of fabrication are provided. A method includes providing a semiconductor structure with a first sidewall distanced from a second sidewall, fins located between the first sidewall and the second sidewall, and isolation regions located between the first sidewall and the second sidewall, wherein adjacent fins are separated by a respective isolation region. The method further includes performing a plasma etching process to etch the fins and the isolation regions, wherein the plasma etching process chemically etches the fins, wherein the plasma etching process physically etches the isolation regions to recesses defining a crown-shaped depth profile.