Patents by Inventor Yi-Fan Chen

Yi-Fan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11437484
    Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chun Chen, Tsung Fan Yin, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu
  • Publication number: 20220270267
    Abstract: Embodiments of the disclosure provide systems and methods for performing occlusion detection in frame rate up-conversion of video data including a sequence of image frames. The method includes determining, by a video processor, whether a target block of a target frame is a potential occlusion block based on at least one of motion vector information or distortion metric information associated with the target block. The target frame is to be generated and interpolated into the sequence of image frames. Responsive to the target block being the potential occlusion block, the method further includes detecting, by the video processor, an occlusion type of the target block. The method additionally includes generating, by the video processor, the target block by performing a motion compensation method adaptively selected based on the occlusion type of the target block.
    Type: Application
    Filed: February 1, 2022
    Publication date: August 25, 2022
    Applicant: Beijing Dajia Internet Information Technology Co., Ltd.
    Inventors: Shuiming Ye, Xianglin Wang, Yi-Wen Chen, Guoxin Jin, Shufei Fan, Bing Yu
  • Publication number: 20220249209
    Abstract: An oral scanner including a heating element, a reflecting element and a temperature difference generating element is provided. The temperature difference generating element has a high temperature end and a low temperature end. The high temperature end is connected to the reflecting element to heat the reflecting element, and the low temperature end is connected to the heating element to cool the heating element.
    Type: Application
    Filed: January 24, 2022
    Publication date: August 11, 2022
    Applicant: Qisda Corporation
    Inventors: Chien-Hung LIN, Po-Fu WU, Jun-Ming SHEN, Szu-Fan CHEN, Yi-Ling LO
  • Patent number: 11392174
    Abstract: Examples of communication of clocking apparatuses with computing devices are described. In an example implementation, a docking device and a computing device communicate through a Universal Serial Bus (USB) port of a USB hub of the docking device in USB Alternate Mode based on USB protocol-based messages.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: July 19, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Yi-Fan Hsia, Hui-Ying Yang, Hung Lung Chen
  • Publication number: 20220223710
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
    Type: Application
    Filed: March 30, 2022
    Publication date: July 14, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Publication number: 20220210467
    Abstract: According to one aspect of the disclosure, a computer-implemented method for performing frame rate up-conversion of video data including a sequence of image frames is provided. The method may include performing, by a video processor, an interpolation quality reliability prediction for a target image level based on a reliability metric. In response to the interpolation quality reliability prediction meeting a first reliability threshold condition associated with a first reliability threshold, the method may include performing, by the video processor, a motion-compensation interpolation at the target image level. In response to the interpolation quality reliability prediction not meeting the first reliability threshold, the method may include performing, by the video processor, a fallback interpolation at the target image level or performing a new interpolation quality reliability prediction for a new image level below the target image level.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 30, 2022
    Applicant: BEIJING DAJIA INTERNET INFORMATION TECHNOLOGY CO., LTD.
    Inventors: Yi-Wen Chen, Xianglin Wang, Shuiming Ye, Guoxin Jin, Shufei Fan, Bing Yu
  • Patent number: 11361701
    Abstract: The present disclosure relates to a driving circuit including a pulse amplitude modulation (PAM) circuit and a pulse width modulation (PWM) circuit. The PAM circuit includes a first transistor, a first capacitor, and a second transistor. The PWM circuit includes a second capacitor, a third transistor, and a fourth transistor. The first capacitor's first terminal is connected to the first transistor's gate. The second transistor's first terminal is connected to the first capacitor's first terminal, and the second transistor's second terminal is connected to the first transistor's second terminal. The third transistor's gate is connected to the second capacitor's second terminal. The fourth transistor's first terminal is connected to the third transistor's gate, the fourth transistor's second terminal is connected to the third transistor's second terminal, and the fourth transistor's gate is connected to the second transistor's gate and configured to receive a first control signal.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: June 14, 2022
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Che-Wei Tung, Shang-Jie Wu, Yu-Chieh Kuo, Yu-Hsun Chiu, Che-Chia Chang, Yu-Zuo Lin, Chen-Ying Chou, Yi-Fan Chen
  • Patent number: 11335427
    Abstract: A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating an error indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relation between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.
    Type: Grant
    Filed: November 4, 2020
    Date of Patent: May 17, 2022
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Yu-Tao Lin, Tse-Hua Yao, Yi-Fan Chen
  • Publication number: 20220139479
    Abstract: A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating an error indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relation between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.
    Type: Application
    Filed: November 4, 2020
    Publication date: May 5, 2022
    Inventors: Yu-Tao Lin, Tse-Hua Yao, Yi-Fan Chen
  • Publication number: 20220114947
    Abstract: A driving circuit includes a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a regulator circuit. The first transistor, the second transistor and the light-emitting element are coupled in series between a first system voltage terminal and a second system voltage terminal. A first terminal of the first transistor is coupled to the first system voltage terminal. The third transistor is electrically coupled between a gate terminal and a second terminal of the first transistor. The fourth transistor is electrically coupled between the gate terminal of the first transistor and the second system voltage terminal. A first terminal of the first capacitor is electrically coupled to the gate terminal of the first transistor. A regulator circuit is electrically coupled to a second terminal of the first capacitor.
    Type: Application
    Filed: September 8, 2021
    Publication date: April 14, 2022
    Inventors: Che-Chia CHANG, Yi-Jung CHEN, Shang-Jie WU, Yu-Chieh KUO, Hsien-Chun WANG, Ming-Hung CHUANG, Mei-Yi LI, He-Yi CHENG, Yi-Fan CHEN
  • Publication number: 20220059024
    Abstract: A display apparatus includes a substrate and pixels disposed on the substrate. Each of the pixels includes sub-pixels. The substrate has an intermediate region and a peripheral region, where the peripheral region is located between an edge of the substrate and the intermediate region. The pixels include standard pixels disposed in the intermediate region and peripheral pixels disposed in the peripheral region. A color displayed by a sub-pixel of a standard pixel and a color displayed by a sub-pixel of a peripheral pixel are the same, and a distance between a second transistor of the sub-pixel of the standard pixel and a pad of the sub-pixel of the standard pixel is not equal to a distance between a second transistor of the sub-pixel of the peripheral pixel and a pad of the sub-pixel of the peripheral pixel.
    Type: Application
    Filed: November 5, 2021
    Publication date: February 24, 2022
    Applicant: Au Optronics Corporation
    Inventors: Shang-Jie Wu, Yu-Chieh Kuo, He-Yi Cheng, Che-Chia Chang, Yi-Jung Chen, Yi-Fan Chen, Yu-Hsun Chiu, Mei-Yi Li
  • Publication number: 20210373623
    Abstract: A display device and a bezel thereof are provided. The display device includes a display panel and a bezel. The display panel has a first surface and a second surface. The first surface includes at least one pixel pad section, and the second surface includes at least one circuit pad section. The bezel includes a first surface connecting portion, a second surface connecting portion and at least one conductive wire. The edge of the display panel having the pixel pad section and the circuit pad section is accommodated between the first surface connecting portion and the second surface connecting portion. Each conductive wire has a first end and a second end. The first end is disposed on the first surface connecting portion and the second end is disposed on the second surface connecting portion. The part of the first connecting portion having the first end corresponds to the pixel pad section, and the part of the second connecting portion having the second end corresponds to the circuit pad section.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 2, 2021
    Inventors: YI-FAN CHEN, CHE-CHIA CHANG, SHANG-JIE WU, YU-CHIEH KUO, YI-JUNG CHEN, YU-HSUN CHIU, MEI-YI LI, HE-YI CHENG
  • Publication number: 20210359180
    Abstract: A pixel array substrate includes a base, pixel structures, first bonding pads, first wirings, and a first testing element. The pixel structures are disposed on an active area of a first surface of the base. The first bonding pads are disposed on a peripheral region of the first surface. Each of the first wirings is disposed on a corresponding first bonding pad, a first sidewall of the base, and a corresponding second bonding pad. The first testing element is disposed on the active area of the first surface and has a first testing line. The first testing line is electrically connected to at least one of the first bonding pads, and an end of the first testing line is substantially aligned with an edge of the base.
    Type: Application
    Filed: August 31, 2020
    Publication date: November 18, 2021
    Applicant: Au Optronics Corporation
    Inventors: Shang-Jie Wu, Hao-An Chuang, Yu-Chieh Kuo, He-Yi Cheng, Che-Chia Chang, Yi-Jung Chen, Yi-Fan Chen, Yu-Hsun Chiu, Mei-Yi Li, Yu-Chin Wu
  • Patent number: 11170699
    Abstract: A display apparatus includes a substrate and pixels disposed on the substrate. Each of the pixels includes sub-pixels. The substrate has an intermediate region and a peripheral region, where the peripheral region is located between an edge of the substrate and the intermediate region. The pixels include standard pixels disposed in the intermediate region and peripheral pixels disposed in the peripheral region. A color displayed by a sub-pixel of a standard pixel and a color displayed by a sub-pixel of a peripheral pixel are the same, and a distance between a second transistor of the sub-pixel of the standard pixel and a pad of the sub-pixel of the standard pixel is not equal to a distance between a second transistor of the sub-pixel of the peripheral pixel and a pad of the sub-pixel of the peripheral pixel.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: November 9, 2021
    Assignee: Au Optronics Corporation
    Inventors: Shang-Jie Wu, Yu-Chieh Kuo, He-Yi Cheng, Che-Chia Chang, Yi-Jung Chen, Yi-Fan Chen, Yu-Hsun Chiu, Mei-Yi Li
  • Patent number: 11127477
    Abstract: An E-fuse circuit comprising: an E-fuse group, comprising a plurality of E-fuse sections, wherein each one of the E-fuse sections comprises a plurality of E-fuses; a multi-mode latch circuit, configured to receive an input signal to generate a first output signal in a burn in mode, and configured to receive an address to be compared to generate a second output signal in a normal mode; a first logic circuit group, configured to receive a first part of bits of the first output signal to generate a control signal in the burn in mode; and a second logic circuit group, configured to receive the control signal and a second part of bits of the first output signal to generate a selection signal in the burn in mode, to select which one of the E-fuse sections is activated.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: September 21, 2021
    Assignee: Elite Semiconductor Microelectronics Technology Inc.
    Inventors: Tse-Hua Yao, Yi-Fan Chen
  • Publication number: 20210202255
    Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Inventors: Hongfa Luan, Yi-Fan Chen, Chun-Yen Peng, Cheng-Po Chau, Wen-Yu Ku, Huicheng Chang
  • Publication number: 20210151650
    Abstract: A display device includes a substrate and pixels. The substrate has an intermediate region and a peripheral region. Each of the pixels includes sub-pixels. Each of the sub-pixels includes a pad group and a light emitting diode (LED) element. The pad group has a first pad and a second pad. The LED element is electrically connected to the first pad and the second pad. The pixels include standard pixels disposed in the intermediate region and peripheral pixels disposed in the peripheral region. The first pads and the second pads of the pad groups of the sub-pixels of each of the standard pixels are arranged in a first direction. The peripheral pixels include a first peripheral pixel. The first pads and the second pads of the pad groups of the sub-pixels of the first peripheral pixel are arranged in a second direction, and the first direction crosses over the second direction.
    Type: Application
    Filed: September 2, 2020
    Publication date: May 20, 2021
    Applicant: Au Optronics Corporation
    Inventors: Shang-Jie Wu, Yu-Chieh Kuo, He-Yi Cheng, Che-Chia Chang, Yi-Jung Chen, Yi-Fan Chen, Yu-Hsun Chiu, Mei-Yi Li
  • Patent number: 10989732
    Abstract: Wireless piezoelectric accelerometers and systems are provided. A wireless piezoelectric accelerometer may comprise a piezoelectric sensing element configured to sense mechanical acceleration and produce an electrical charge signal in response of the sensed mechanical acceleration, a signal processing module (SPM) configured to convert the electrical charge signal into a voltage signal, and process and digitize the voltage signal, and a wireless module configured to modulate and transmit the digitized voltage signal as wireless signals. The piezoelectric sensing element, the SPM and the wireless module are packaged in a casing. The casing comprises a metallic shielding chamber configured to enclose the piezoelectric sensing element. The casing further comprises a non-metallic portion located in relative to the wireless module to allow transmission of the wireless signals. Corresponding wireless piezoelectric accelerometer systems are also provided.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: April 27, 2021
    Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Kui Yao, Zhiyuan Shen, Chin Yaw Tan, Yi Fan Chen, Lei Zhang
  • Patent number: 10971058
    Abstract: A display apparatus includes pixels, each of which includes first and second pixel driver circuits, first and second driver pads electrically connected to the first and second pixel driver circuits, respectively, a first LED element, first and second connection lines electrically connected to the first and second pixel driver circuits, respectively, and first and second repair pads electrically connected to the first and second connection lines, respectively. A first electrode of the first LED element is electrically connected to the first driver pad. The first repair pad, the second repair pad, the first driver pad, and the second driver pad are structurally separated. A first pixel of the pixels further includes a second LED element overlapping the first and second repair pads of the first pixel, and a first electrode of the second LED element is electrically connected to the second repair pad.
    Type: Grant
    Filed: June 21, 2020
    Date of Patent: April 6, 2021
    Assignee: Au Optronics Corporation
    Inventors: He-Yi Cheng, Yu-Chieh Kuo, Shang-Jie Wu, Che-Chia Chang, Yi-Fan Chen, Yi-Jung Chen, Yu-Hsun Chiu, Mei-Yi Li, Hsin-Chun Huang
  • Patent number: D956081
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: June 28, 2022
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chao-Chieh Cheng, Chia-Fan Hou, Sheng-Ta Lin, Ya-Ting Chen, Chun-Tsai Yeh, Yi-Ou Wang, Chien-Chih Tseng