Abstract: A memory device and an operation method thereof are provided. The memory device includes memory cells, each having a static random access memory (SRAM) cell and a non-volatile memory cell. The SRAM cell is configured to store complementary data at first and second storage nodes. The non-volatile memory cell is configured to replicate and retain the complementary data before the SRAM cell loses power supply, and to rewrite the replicated data to the first and second storage nodes of the SRAM cell after the power supply of the SRAM cell is restored.

Abstract: A method of fabricating an integrated circuit (IC) is provided. The method includes the following steps: providing a substrate; forming a p-well region in the substrate; forming an n-well region in the substrate; conducting a microwave annealing at a first temperature; conducting, after the microwave annealing, a supplemental annealing at a second temperature higher than the first temperature; and fabricating a plurality of field-effect transistors (FETs) in the p-well region and the n-well region.

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

Abstract: An annealing apparatus includes: a first chamber including a first gas having a first gas pressure; a second chamber configured to receive a second gas having a second gas pressure; gas inlets; gas vents; heating elements laterally surrounding the first chamber; and a controller configured to perform the steps of: heating the first chamber while keeping a gas pressure difference between the first gas pressure and the second gas pressure is within a tolerance limit; and cooling the first chamber by exchanging the second gas in the second chamber while keeping the gas pressure difference within the tolerance limit, wherein the exchanging of the second gas includes introducing the second gas to the second chamber through the plurality of gas inlets and exhausting a the second gas out of the second chamber through the plurality of gas vents while keeping the second gas pressure unchanged.

Abstract: The present disclosure relates to computer-implemented systems and methods for sharing, managing, and executing computer simulations via a simulation service. In one particular embodiment, the simulation service is stored and executed on a remote computing device wherein the simulation service and remote computing device are configured to interface with client devices or programs. In some instances, input data and configuration parameters may be sent from the client devices or programs to the remote computing device to execute a given computer simulation, and the results may be returned to the client devices or programs as they become available.

Abstract: An inverter device includes a converter circuit and a filter. The converter circuit converts a DC input voltage into an AC intermediate voltage based on six control signals, and includes first and second converters. Each of the first and second converters includes three switches, two diodes and a coupled inductor circuit. The switches of the first converter operate respectively based on three of the control signals. The switches of the second converter operate respectively based on the other three of the control signals. The filter filters the AC intermediate voltage to generate an AC output voltage.

Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.

Abstract: A method of forming a semiconductor device includes forming a sacrificial gate structure over a substrate, depositing a spacer layer on the sacrificial gate structure in a conformal manner, performing a multi-step oxidation process to the spacer layer, etching the spacer layer to form gate sidewall spacers on opposite sidewalls of the sacrificial gate structure, removing the sacrificial gate structure to form a trench between the gate sidewalls spacers, and forming a metal gate structure in the trench.

Abstract: A display device includes a substrate and pixels. The substrate has an intermediate region and a peripheral region. Each of the pixels includes sub-pixels. Each of the sub-pixels includes a pad group and a light emitting diode (LED) element. The pad group has a first pad and a second pad. The LED element is electrically connected to the first pad and the second pad. The pixels include standard pixels disposed in the intermediate region and peripheral pixels disposed in the peripheral region. The first pads and the second pads of the pad groups of the sub-pixels of each of the standard pixels are arranged in a first direction. The peripheral pixels include a first peripheral pixel. The first pads and the second pads of the pad groups of the sub-pixels of the first peripheral pixel are arranged in a second direction, and the first direction crosses over the second direction.

Abstract: A driving circuit includes a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a regulator circuit. The first transistor, the second transistor and the light-emitting element are coupled in series between a first system voltage terminal and a second system voltage terminal. A first terminal of the first transistor is coupled to the first system voltage terminal. The third transistor is electrically coupled between a gate terminal and a second terminal of the first transistor. The fourth transistor is electrically coupled between the gate terminal of the first transistor and the second system voltage terminal. A first terminal of the first capacitor is electrically coupled to the gate terminal of the first transistor. A regulator circuit is electrically coupled to a second terminal of the first capacitor.

Abstract: A display apparatus includes a substrate and pixels disposed on the substrate. Each of the pixels includes sub-pixels. The substrate has an intermediate region and a peripheral region, where the peripheral region is located between an edge of the substrate and the intermediate region. The pixels include standard pixels disposed in the intermediate region and peripheral pixels disposed in the peripheral region. A color displayed by a sub-pixel of a standard pixel and a color displayed by a sub-pixel of a peripheral pixel are the same, and a distance between a second transistor of the sub-pixel of the standard pixel and a pad of the sub-pixel of the standard pixel is not equal to a distance between a second transistor of the sub-pixel of the peripheral pixel and a pad of the sub-pixel of the peripheral pixel.

Abstract: A method includes: transporting a wafer to an apparatus, the apparatus including: a first chamber configured to receive the wafer and a first gas; a second chamber surrounding the first chamber and configured to receive a second gas; a plurality of gas inlets on a chamber wall of the second chamber; and a plurality of gas vents on the chamber wall of the second chamber; heating the first chamber while keeping a gas pressure difference between the first chamber and the second chamber within a tolerance limit; and cooling the first chamber by exchanging the second gas in the second chamber while keeping the gas pressure difference within the tolerance limit.

Abstract: An inverter device includes a converter circuit and a filter. The converter circuit converts a DC input voltage into an AC intermediate voltage based on six control signals, and includes first and second converters. Each of the first and second converters includes three switches, two diodes and a coupled inductor circuit. The switches of the first converter operate respectively based on three of the control signals. The switches of the second converter operate respectively based on the other three of the control signals. The filter filters the AC intermediate voltage to generate an AC output voltage.

Abstract: A pixel array substrate includes a base, pixel structures, first bonding pads, first wirings, and a first testing element. The pixel structures are disposed on an active area of a first surface of the base. The first bonding pads are disposed on a peripheral region of the first surface. Each of the first wirings is disposed on a corresponding first bonding pad, a first sidewall of the base, and a corresponding second bonding pad. The first testing element is disposed on the active area of the first surface and has a first testing line. The first testing line is electrically connected to at least one of the first bonding pads, and an end of the first testing line is substantially aligned with an edge of the base.

Abstract: A method includes placing a wafer on a susceptor, wherein the wafer has a first radius, wherein a top surface of the susceptor has a second radius that is greater than the first radius; using microwave radiation to heat the wafer and the susceptor; and removing the wafer from the susceptor.

Abstract: The present disclosure relates to a driving circuit including a pulse amplitude modulation (PAM) circuit and a pulse width modulation (PWM) circuit. The PAM circuit includes a first transistor, a first capacitor, and a second transistor. The PWM circuit includes a second capacitor, a third transistor, and a fourth transistor. The first capacitor's first terminal is connected to the first transistor's gate. The second transistor's first terminal is connected to the first capacitor's first terminal, and the second transistor's second terminal is connected to the first transistor's second terminal. The third transistor's gate is connected to the second capacitor's second terminal. The fourth transistor's first terminal is connected to the third transistor's gate, the fourth transistor's second terminal is connected to the third transistor's second terminal, and the fourth transistor's gate is connected to the second transistor's gate and configured to receive a first control signal.

Abstract: A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating an error indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relation between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.

Abstract: A memory test circuit comprising: a first latch circuit for receiving a first input address and an error indication signal to generate a first address; a first E-fuse group for receiving the first address to generate an output address; a second latch circuit for receiving the error indication signal; a second E-fuse group for generating an error indication signal according to an output of the second latch circuit which is generated according to the fault indication signal; and a comparison circuit for activating the second latch circuit according to a relation between the first address and a second input address and a state of the first latch circuit or the first E-fuse group.

Abstract: A driving circuit includes a light-emitting element, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor and a regulator circuit. The first transistor, the second transistor and the light-emitting element are coupled in series between a first system voltage terminal and a second system voltage terminal. A first terminal of the first transistor is coupled to the first system voltage terminal. The third transistor is electrically coupled between a gate terminal and a second terminal of the first transistor. The fourth transistor is electrically coupled between the gate terminal of the first transistor and the second system voltage terminal. A first terminal of the first capacitor is electrically coupled to the gate terminal of the first transistor. A regulator circuit is electrically coupled to a second terminal of the first capacitor.

Abstract: A display apparatus includes a substrate and pixels disposed on the substrate. Each of the pixels includes sub-pixels. The substrate has an intermediate region and a peripheral region, where the peripheral region is located between an edge of the substrate and the intermediate region. The pixels include standard pixels disposed in the intermediate region and peripheral pixels disposed in the peripheral region. A color displayed by a sub-pixel of a standard pixel and a color displayed by a sub-pixel of a peripheral pixel are the same, and a distance between a second transistor of the sub-pixel of the standard pixel and a pad of the sub-pixel of the standard pixel is not equal to a distance between a second transistor of the sub-pixel of the peripheral pixel and a pad of the sub-pixel of the peripheral pixel.