Abstract: The present invention relates to a method and a device for adaptive color correction by weighting procedure according to the pixel luminance so as to adjust the pixel chrominance. The present invention prevents color noise occurring in the dark pictures.

Abstract: The present invention provides a method for reducing-plasma damage to a gate oxide of a metal-oxide semiconductor (MOS) transistor positioned on a substrate of a MOS semiconductor wafer. The method begins with the formation of a dielectric layer covering the MOS transistor on the substrate. An etching process is then performed to form a first contact hole through the dielectric layer to a gate on the surface of the MOS transistor, as well as to form a second contact hole through the dielectric layer to an n-well in the substrate. A bypass circuit, positioned on the dielectric layer and the first and second contact holes, and a fusion area are then formed. The fusion area, electrically connecting with the bypass circuit, also electrically connects with the MOS transistor and the n-well thereafter. Ions produced during the process are thus transferred to the n-well via the conductive wire so as to reduce plasma damage to the gate oxide.

Abstract: A method for driving a liquid crystal display panel is disclosed. The liquid crystal display panel has a plurality of scan lines, a plurality of data lines, and a plurality of pixels. Each pixel is connected to a corresponding scan line and a corresponding data line, and each pixel has a liquid crystal element and a switching device connected to the corresponding scan line, the corresponding data line, and the liquid crystal element. The method sequentially receives a plurality of pieces of frame data and generates at least one over-drive data impulse and an original data impulse for each pixel every frame period according to the pieces of the frame data. The over-drive data impulse and the original data impulse are applied to the data line connected to the liquid crystal element of the pixel within one frame period.

Abstract: A method for luminance compensation of liquid crystal display includes: measuring the original gamma curve of the panel, setting a target gamma curve, inputting an initial gray level to obtain a luminance corresponding to the target gamma curve, finding the adjusted gray level for expressing the luminance from the original gamma curve, repeating the steps stated above to make a lookup table containing plural groups of proportion array. Then calculating the quantity distribution of input gray levels of images, selecting a corresponding proportion array from the lookup table according to the proportion value between dark level and bright level, substituting the adjusted gray levels in the proportion array for the input gray levels, outputting the adjusted gray levels for adjusting the signal intensity can improve the image quality.

Abstract: A color correction circuit and a color correction method for a liquid crystal display, the circuit comprises a color selection unit, a parameter register unit, a color signal function calculation unit and a color signal output unit. The method is characterized in providing selection items of measuring values of color temperature values and Gamma values and providing a correction parameter value obtained by function calculation, being in corresponding to a selected selection item. A user can correct a color signal according to the color correction circuit and the method. This is applicable to color signal adjustment for liquid crystal panels.

Abstract: The present invention utilizes to wafer acceptance testing equipment to fast monitor the quality of a tunnel oxide layer. First, a control gate and a floating gate in a memory cell are electrically connected. Then a plurality of swing time-dependent DC ramping voltages are applied and each corresponding gate leakage current is measured to calculate each corresponding ? value. Finally a ratio of each ? value is calculated and a ?-gate voltage curve is plotted to actually simulate the device failure.

Abstract: A bump structure of a scattering reflective board and a method for manufacturing the bump structure. Multiple strip-shaped shielding sections are arranged on an optical mask at intervals. Multiple irregularly arranged circular holes are distributed in the respective strip-shaped shielding sections. Multiple irregularly arranged circular shielding sections are distributed in spacing sections between the adjacent strip-shaped shielding sections. Multiple irregularly arranged arch notches and arch shielding sections are distributed on the edges of the strip-shaped shielding sections. After exposed and developed, multiple scattered and irregularly arranged bumps are formed on the photosensitive material layer laid on the substrate. Then a reflective film is laid on the substrate and the bumps to form the reflective board.

Abstract: A liquid crystal display (LCD) device and a driving method thereof are disclosed. In order to obtain high-quality images, a signal preprocessor is incorporated in the gray signal modulator of conventional LCDs. The signal preprocessor can be specifically designed as a noise-reduction preprocessor for suppressing the noise induced from the input gray signals, or designed for detecting a certain character of input gray signals for further processes. After be processed by the signal preprocessor, optimized modified gray signals can be obtained from the signal converter for driving the LCD, thereby producing high-quality images.

Abstract: The present invention utilizes wafer acceptance testing equipment to fast monitor the quality of an insulation layer. A plurality of swing time-dependent DC ramping voltages are applied to one of the electrode plates in a capacitor and each corresponding leakage current is measured to calculate each corresponding ? value. Then, a ratio of each ? value is calculated and a ?? voltage curve is plotted to actually simulate the device failure.

Abstract: A bump structure of a scattering reflective board and a method for manufacturing the bump structure. Multiple strip-shaped shielding sections are arranged on an optical mask at intervals. Multiple irregularly arranged circular holes are distributed in the respective strip-shaped shielding sections. Multiple irregularly arranged circular shielding sections are distributed in spacing sections between the adjacent strip-shaped shielding sections. Multiple irregularly arranged arch notches and arch shielding sections are distributed on the edges of the strip-shaped shielding sections. After exposed and developed, multiple scattered and irregularly arranged bumps are formed on the photosensitive material layer laid on the substrate. Then a reflective film is laid on the substrate and the bumps to form the reflective board.

Abstract: Nano structures are formed in a glass layer on a substrate by defining a first structure in the glass layer using a low energy radiation exposure, and then defining a second structure in the glass layer for the dynamic layer using a higher energy radiation exposure. The structures are then developed in TMAH. The structures include at least sensors and nano-channels. Densification is performed by converting the structures to SiO2. Further structures are formed by using different energy exposures. One structure is a channel having a porous wall prior to development.

Abstract: Nano structures are formed in a glass layer on a substrate by defining a first structure in the glass layer using a low energy radiation exposure, and then defining a second structure in the glass layer for the dynamic layer using a higher energy radiation exposure. The structures are then developed in TMAH. The structures include at least sensors and nano-channels. Densification is performed by converting the structures to SiO2. Further structures are formed by using different energy exposures. One structure is a channel having a porous wall prior to development.

Abstract: The present invention utilizes a wafer acceptance testing equipment to fast monitor the quality of a tunnel oxide layer. First, a control gate and a floating gate in a memory cell are electrically connected. Then a plurality of swing time-dependent DC ramping voltages are applied and each corresponding gate leakage current is measured to calculate each corresponding &bgr; value. Finally a ratio of each &bgr; value is calculated and a &bgr;-gate voltage curve is plotted to actually simulate the device failure.

Abstract: A color compensating structure of semireflecting liquid crystal display and a method for manufacturing the structure. A structure includes an upper insulating substrate and a lower insulating substrate between which a liquid crystal layer is disposed. A semireflecting film is plated on the lower insulating substrate. A color light filtering film and a resin protective layer are sequentially disposed on the semireflecting film. The color light filtering film is formed of light resistor with high color saturation. A total reflecting film is plated on the protective layer and patterned.

Abstract: The present invention provides a method for reducing plasma damage to a gate oxide of a metal-oxide semiconductor (MOS) transistor positioned on a substrate of a MOS semiconductor wafer. The method begins with the formation of a dielectric layer covering the MOS transistor on the substrate. An etching process is then performed to form a first contact hole through the dielectric layer to a gate on the surface of the MOS transistor, as well as to form a second contact hole through the dielectric layer to an n-well in the substrate. A bypass circuit, positioned on the dielectric layer and the first and second contact holes, and a fusion area are then formed. The fusion area, electrically connecting with the bypass circuit, also electrically connects with the MOS transistor and the n-well thereafter. Ions produced during the process are thus transferred to the n-well via the conductive wire so as to reduce plasma damage to the gate oxide.

Abstract: The present invention provides a method for reducing plasma damage to a gate oxide of a metal-oxide semiconductor (MOS) transistor positioned on a substrate of a MOS semiconductor wafer. The method begins with the formation of a dielectric layer covering the MOS transistor on the substrate. An etching process is then performed to form a first contact hole through the dielectric layer to a gate on the surface of the MOS transistor, as well as to form a second contact hole through the dielectric layer to an n-well in the substrate. A bypass circuit, positioned on the dielectric layer and the first and second contact holes, and a fusion area are then formed. The fusion area, electrically connecting with the bypass circuit, also electrically connects with the MOS transistor and the n-well thereafter. Ions produced during the process are thus transferred to the n-well via the conductive wire so as to reduce plasma damage to the gate oxide.

Abstract: A tetra-ethyl-ortho-silicate (TEOS) layer is first deposited on the surface of a MOS transistor followed by the deposition of a borophosposilicate glass (BPSG) layer atop the TEOS layer. Thereafter, an ion implantation process of BF2+ is performed to alter the dopant concentration in the gate conduction layer of the PMOS transistor. Both the TEOS layer and the BPSG layer suppress both free fluorine and boron ions from entering the gate during the ion implantation process of BF2+ to prevent boron penetration of the MOS transistor and stabilize the threshold voltage of the MOS transistor.

Abstract: The present invention provides a method for reducing plasma damage to a gate oxide of a metal-oxide semiconductor (MOS) transistor positioned on a substrate of a MOS semiconductor wafer. The method begins with the formation of a dielectric layer covering the MOS transistor on the substrate. An etching process is then performed to form a first contact hole through the dielectric layer to a gate on the surface of the MOS transistor, as well as to form a second contact hole through the dielectric layer to an n-well in the substrate. A bypass circuit, positioned on the dielectric layer and the first and second contact holes, and a fusion area are then formed. The fusion area, electrically connecting with the bypass circuit, also electrically connects with the MOS transistor and the n-well thereafter. Ions produced during the process are thus transferred to the n-well via the conductive wire so as to reduce plasma damage to the gate oxide.

Abstract: A method for forming a dielectric layer with uniform thickness in a trench capacitor comprises providing a substrate structure. A trench device formed in the substrate structure is used as a capacitor and has sidewall and a bottom. Next, the sidewall of the trench device are treated by ion bombardment for forming amorphous structure thereon. Then a dielectric layer, such as an oxide layer, is formed on the sidewall and the bottom of the trench device by CVD or thermal oxidation. To be specific, because of amorphous structure of the sidewall and bottom of the trench device, the dielectric layer can have uniform thickness profile in the trench device.

Abstract: A method for reducing static power dissipation in a semiconductor device is provided. The method is characterized in that utilizing a simple control device connecting with a MOS device, serving for a drain voltage controller, instead of the conventional voltage supply directly connected with the drain. The control device comprises two input terminals and an output terminal. One of the two input terminals is connected with a voltage supply, the other of the two input terminals is connected with a control signal. The output terminal of the control device is connected to the drain of the MOS device. When the control signal is activated, the output terminal of the control device is grounded and thus the drain is grounded. Thereby, all of the possible leakage paths induced by the drain voltage are inhibited. While the control signal is un-activated, the output terminal of the control device provides a supply voltage to the drain.