Patents by Inventor Yi Hui

Yi Hui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240032439
    Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 25, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, JUN XIE
  • Publication number: 20240027811
    Abstract: A display device, including a first display panel, a second display panel, and a first optical structure layer, is provided. The first display panel has a first display surface emitting light toward a first direction. The second display panel has a second display surface emitting light toward a second direction, wherein the first direction is different from the second direction. The first optical structure layer is disposed on the first display panel, wherein a glossiness of the first optical structure layer is between 4 GU and 35 GU, and a reflectivity of specular component included (SCI) of the first optical structure layer is between 3% and 6%. The display device provided by the disclosure can reduce the influence of ambient light from the outside on a displayed image.
    Type: Application
    Filed: June 8, 2023
    Publication date: January 25, 2024
    Applicant: Innolux Corporation
    Inventors: Yu-Chun Hsu, Wei-Ming Chu, Yi-Hui Lee, Yung-Chih Cheng, Kuan-Chou Chen, Sheng-Nan Fan
  • Publication number: 20240016357
    Abstract: A robotic cleaning system may include a docking station, a robotic cleaner that includes at least one of a first set of robot charging contacts or a second set of robot charging contacts, the first and second sets of robot charging contacts being configured to electrically couple the robotic cleaner to the docking station, a dust cup configured to removably couple to the robotic cleaner, and a mop module configured to removably couple to the robotic cleaner. When the mop module is coupled to the robotic cleaner, the robotic cleaner may be configured to electrically couple to the docking station using the first set of robot charging contacts. When the mop module is not coupled to the robotic cleaner, the robotic cleaner may be configured to electrically couple to the docking station using the second set of robot charging contacts.
    Type: Application
    Filed: August 17, 2022
    Publication date: January 18, 2024
    Inventors: Simon HUGHES, Zhanglin Liu, Yi hui ZHANG, Yafei Shen, Wulin Tian, Scott TEUSCHER, John LEWIS, Hamish THOMPSON
  • Publication number: 20240016356
    Abstract: A robotic cleaner may include one or more driven wheels, at least one environmental sensor, and a mop module. The mop module may include a tank having a tank inlet and a tank outlet, a pad coupled at a bottom side of the tank, the pad configured to contact a surface to be cleaned and to receive liquid from the tank outlet, and a latch configured to transition between a latched position, a release position, and a refill position. When in the latched position and in the release position, at least a portion of the latch may extend over the tank inlet and, when in the refill position, the latch may be displaced from the tank inlet, exposing the tank inlet.
    Type: Application
    Filed: August 17, 2022
    Publication date: January 18, 2024
    Inventors: Jun Feng DING, Evan P. JASPER, Yi hui ZHANG, Hamish THOMPSON, Max DAVIDOWITZ, Simon HUGHES, Jianjun GE, Jian XIANG
  • Patent number: 11854018
    Abstract: A method, computer system, and a computer program product for labeling optimization is provided. The present invention may include receiving a plurality of labeled historical transaction timeline image clusters based on a plurality of historical transaction timeline images clustered using unsupervised machine learning. The present invention may further include training an image recognition model using supervised machine learning based on the received plurality of labeled historical transaction timeline image clusters. The present invention may also include receiving, by the trained image recognition model, a current transaction timeline image. The present invention may further include assigning a corresponding label to the received current transaction timeline image based on matching the received current transaction timeline image to one of the received plurality of labeled historical transaction timeline image clusters.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: December 26, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Willie Robert Patten, Jr., Eugene Irving Kelton, Yi-Hui Ma, Brandon Harris
  • Patent number: 11849648
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: December 19, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
  • Publication number: 20230380072
    Abstract: A manufacturing method of tape includes the steps of providing a tape including substrate units, providing a die device and a cutting and/or pressing process. Each of the substrate units includes a carrier, a circuit layer, an adhesive and a heat spreader, the heat spreader is attached onto the carrier by the adhesive. In the cutting and/or pressing process, the die device is provided to press the tape to generate separation protrusions on the heat spreader and allow the separation protrusions to protrude from a heat dissipation surface of the heat spreader. When rolling the tape, the separation protrusions can separate the stacked substrate units to prevent the adhesive from being squeezed out to contaminate the tape.
    Type: Application
    Filed: February 14, 2023
    Publication date: November 23, 2023
    Inventors: Yi-Hui Chen, Yi-Hua Huang, Yen-Ping Huang, Shih-Chieh Chang
  • Publication number: 20230380296
    Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
    Type: Application
    Filed: August 4, 2023
    Publication date: November 23, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chiu-Jung Chiu, Ya-Sheng Feng, I-Ming Tseng, Yi-An Shih, Yu-Chun Chen, Yi-Hui Lee, Chung-Liang Chu, Hsiu-Hao Hu
  • Patent number: 11823216
    Abstract: Computer vision and deep learning techniques are leveraged to detect behavior patterns in transaction histories. A transaction timeline is built for a series of transactions, e.g., financial, and a graphic image is constructed representing the transaction timeline. The graphic image is then matched to a known behavior pattern using a cognitive system. The cognitive system is trained with historical timeline images having associated labels. In one example the graphic image is a bar chart and each financial transaction is represented as a bar in the bar chart having a height proportional to a transaction amount, the bar being located along a time axis of the bar chart according to the transaction date and being color coded according to the transaction type.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: November 21, 2023
    Assignee: International Business Machines Corporation
    Inventors: Eugene I. Kelton, Brandon Harris, Willie R. Patten, Jr., Eliza Salkeld, Russell Gregory Lambert, Yi-Hui Ma, Shuyan Lu, Shanna Hayes
  • Publication number: 20230358686
    Abstract: An optical detection device includes a base, a cartridge placing portion, a shield cover, a processor, and an optical sensor. The base includes an opening. The cartridge placing portion is located in the base, and is in communication with the opening. The shield cover is configured to open or close the opening. When the optical sensor is actuated, the shield cover closes the opening to prevent external ambient light from entering the opening to affect the optical sensor during sensing.
    Type: Application
    Filed: September 23, 2022
    Publication date: November 9, 2023
    Inventors: Yi-Hui Chen, Chen-Fa Wang
  • Patent number: 11812669
    Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: November 7, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
  • Publication number: 20230310532
    Abstract: The present invention relates, in general terms, to a method of extracting resin glycoside from a plant selected from the Convolvulaceae family. The resin glycosides can be extracted from Ipomoea batatas and/or Ipomoea aquatica. The present invention also relates to the extracts and edible compositions thereof and its use in weight loss and weight management.
    Type: Application
    Filed: April 13, 2021
    Publication date: October 5, 2023
    Inventors: Zhixuan SONG, Dejian HUANG, Yi Hui Joanne TOY, Yi LIN
  • Publication number: 20230314693
    Abstract: A double-sided display device includes a first panel, a second panel, a light guide plate and a light source. The second panel is arranged opposite to the first panel. The light guide plate is arranged between the first panel and the second panel, and includes a main body portion including a first surface and a second surface, a first pattern arranged on the first surface, and a second pattern arranged on the second surface. The light source is arranged adjacent to the light guide plate. The first pattern is different from the second pattern.
    Type: Application
    Filed: February 28, 2023
    Publication date: October 5, 2023
    Inventors: Yi-Hui LEE, Kuan-Chou CHEN, Yung-Chih CHENG
  • Patent number: 11765983
    Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: September 19, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chiu-Jung Chiu, Ya-Sheng Feng, I-Ming Tseng, Yi-An Shih, Yu-Chun Chen, Yi-Hui Lee, Chung-Liang Chu, Hsiu-Hao Hu
  • Patent number: 11748453
    Abstract: Technical solutions are described for improving the performance of natural language processing systems and other such human-computer interaction systems by facilitating analyzing unstructured computer text by converting such unstructured computer text to domain-specific groups using network graphs. The technical solutions use a graph to connect similar terms with attributes and structural information to facilitate the grouping of different terms that may be used to describe the same entity. Technical solutions facilitate analyzing different input data to generate a graph that can be further used to find data similarity in the input data. The generated graph captures attributes associated with each term and assigns groupings for all the terms at the same time, improving the performance of the natural language processing (NLP) system that is analyzing the input data.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: September 5, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yi-Hui Ma, Iman Johari, Vyoma Gajjar
  • Publication number: 20230238043
    Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.
    Type: Application
    Filed: March 28, 2023
    Publication date: July 27, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
  • Patent number: 11711381
    Abstract: A computer-implemented method to automatically identify hotspots in a network graph. The method includes receiving, by a processor, input data, wherein the input data includes a plurality of messages, each message containing a set of message data. The method further includes generating, by a pattern detector, and based on the input data, a network graph, wherein the network graph includes a plurality of nodes. The method also includes determining a first risk indicator for each of the plurality of nodes. The method includes assigning a first weight to the first risk indicator for each of the plurality of nodes. The method further includes identifying a first hotspot in the plurality of nodes, wherein the first hotspot is based on the first weight of the first risk indicator of a first node. The method also includes outputting, by a network interface, the first hotspot and the network graph.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: July 25, 2023
    Assignee: International Business Machines Corporation
    Inventors: Srinivasan S. Muthuswamy, Subhendu Das, Mukesh Kumar, Yi-Hui Ma
  • Publication number: 20230220350
    Abstract: Accordingly. the present disclosure provides a population of genetically engineered mesenchymal stem cells (MSCs), comprising an expression vector comprising an Akt or HGF gene and a PD-L1 gene. Also provided is a method for synergistically increasing survival status and immunomodulatory ability of an MSC or enhancing proliferation of an MSC, comprising transfecting an MSC with an Akt or HGF gene and a PD-L1 gene and a method for preventing, ameliorating and/or treating an ischemia condition, enhancing neuroregeneration or reducing neuronal death, comprising administering an effective amount of a population of genetically engineered MSCs of the present disclosure to a subject in need thereof.
    Type: Application
    Filed: September 27, 2020
    Publication date: July 13, 2023
    Inventors: Woei-Cherng SHYU, Chien-Lin CHEN, Yi-Hui LEE, Long-Bin JENG, Chang-Hai TSAI
  • Patent number: 11648502
    Abstract: A cylindrical filter device of the present invention includes a wavy filter screen, a sealing device, and a connecting device. The wavy filter screen includes a first flexible side strip, a second flexible side strip opposite to the first flexible side strip, and a plurality of wavy structures disposed between the first flexible side strip and the second flexible side strip. The wavy filter screen wraps to form a cylindrical structure with respect to an axis. The opposite ends of the cylindrical structure are respectively wrapped to form a first opening and a second opening by the first flexible side strip and the second flexible side strip. The sealing device is disposed at the first opening and has a first groove. The first flexible side strip is able to engage with the first groove with its elasticity and makes the first opening be sealed by the sealing device. The connecting device is disposed at the second opening. The connecting device has a second groove and a port.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: May 16, 2023
    Assignee: GREENFILTEC LTD.
    Inventor: Yi-Hui Yu
  • Patent number: 11646069
    Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: May 9, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin