Abstract: The present application relates to systems for updating detection models and methods for using the same. The systems and methods generally comprise at least one local node comprising a monitoring module, a diagnosis module, and an evaluation module The system receives at least one model update, and analyzes the model update and current models and data present in the local node, and determines if the update should be applied. In some embodiments, a local node can generate a model update for use in other local nodes, while not sharing private data present in the local node.

Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.

Abstract: The present application relates to systems for updating detection models and methods for using the same. The systems and methods generally comprise at least one local node comprising a monitoring module, a diagnosis module, and an evaluation module The system receives at least one model update, and analyzes the model update and current models and data present in the local node, and determines if the update should be applied. In some embodiments, a local node can generate a model update for use in other local nodes, while not sharing private data present in the local node.

Abstract: Computer vision and deep learning techniques are leveraged to detect behavior patterns in transaction histories. A transaction timeline is built for a series of transactions, e.g., financial, and a graphic image is constructed representing the transaction timeline. The graphic image is then matched to a known behavior pattern using a cognitive system. The cognitive system is trained with historical timeline images having associated labels. In one example the graphic image is a bar chart and each financial transaction is represented as a bar in the bar chart having a height proportional to a transaction amount, the bar being located along a time axis of the bar chart according to the transaction date and being color coded according to the transaction type.

Abstract: A local node for updating detection models while maintaining data privacy has a sharing module configured to receive instructions for calculating at least one general feature from data stored at the first local node, a retraining module configured to retrain the detection model to include a detection component that uses the instructions, a data collection module configured to collect data comprising customer data and transaction data stored at the first local node, and a performance module. The performance module is configured to determine a value for the at least one general feature from the collected data using the instructions, and trigger a suspicious activity alert based on the determined value and the instructions. The customer data and transaction data are indeterminable from the at least one general feature and the determined value.

Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.

Abstract: An approach is provided that automatically computes a number of feature combinations based on a set of subject matter fields that are selected from a set of subject matter fields and further based on qualifiers that correspond to the selected set of subject matter fields. A model in an artificial intelligence (AI) system is then trained using the computed plurality of feature combinations.

Abstract: The technology employs a contrasting color scheme on different surfaces for sensor housing assemblies mounted on exterior parts of a vehicle that is configured to operate in an autonomous driving mode. Lighter and darker colors may be chosen on different surfaces according to a thermal budget for a given sensor housing assembly, due to the different types of sensors arranged along particular surfaces, or to provide color contrast for different regions of the assembly. For instance, differing colors such as black/white or blue/white, and different finishes such as matte or glossy, may be selected to enhance certain attributes or to minimize issues associated with a sensor housing assembly.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

Abstract: A non-volatile memory structure including a substrate, a plurality of charge storage layers, a first dielectric layer, and a control gate is provided. The charge storage layers are located on the substrate. An opening is provided between two adjacent charge storage layers. The first dielectric layer is located on the charge storage layers and on a surface of the opening. A bottom cross-sectional profile of the first dielectric layer located in the opening is a profile that is recessed on both sides. The control gate is located on the first dielectric layer and fills the opening.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.

Abstract: Disclosed is glue-free airtight filtering equipment comprising a filter housing, a plurality of filter elements and a plurality of receiving supporting elements, each filter element having a filtering surface, the plurality of filter elements being detachably disposed in the filtering space in a manner that the filtering surface is parallel to the upper surface and the bottom surface of the filter housing, and the plurality of receiving supporting elements allocating on an inner wall of the filter housing and being spaced apart from each other with a designated distance so as to correspondingly receive and support the plurality of filter elements, wherein a gap is provided between the filter element and the inner wall of the filter housing, and the filtering surface of the filter element and the maximum value of the gap satisfy a relational expression.

Abstract: A MRAM includes a plurality of memory cells, an operation unit, a voltage generator, and an input/output circuit. The operation unit includes multiple groups of memory cells among the plurality of memory cells. The voltage generator is configured to provide a plurality of control signals by voltage-dividing a voltage control signal and selectively output the plurality of control signals to the input/output circuit. The input/output circuit is configured to output a plurality of switching pulse signals to the multiple groups of memory cells according to the plurality of control signals, wherein each switching pulse signal differs in pulse width or level.

Abstract: A local node for updating detection models while maintaining data privacy has an aggregation module, a retraining module, an instructions module, and a sharing module. The aggregation module aggregates the data into features that describe the contents of the data. The retraining module retrains the detection model using the features by implementing an algorithm that includes at least one selected feature and a threshold for triggering an activity alert. The instructions module determines instructions for calculating the at least one selected feature from a different collection of data. The sharing module generates a package having the instructions for calculating the at least one selected feature from the different collection of data and the threshold, and transmits the package to a local node for implementation of the retrained detection model with data stored at the local node.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.

Abstract: A display device includes a first substrate, a first active element layer, first to third light-emitting elements, a first pixel defining layer, and fourth to sixth light-emitting elements. The first active element layer is disposed on the first substrate. The first, second and third light-emitting elements are electrically connected with the first active element layer. The first, second and third light-emitting elements have first, second and third light-emitting layers respectively. The first pixel defining layer is disposed on the first active element layer and has first, second and third openings. The first, second and third light-emitting layers are disposed in the first, second and third openings respectively. The fourth, fifth and sixth light-emitting elements are disposed on the first pixel defining layer. A vertical distance between the first light-emitting element and the fourth light-emitting element is greater than 0 micrometers and less than or equal to 5 micrometers.

Abstract: The present invention relates to a method of manufacturing a power device and a structure of the power device, which is used to solve the problem that conventional power device needs to be independently packaged and requires a welding process. The method includes: forming a plurality of semiconductor device layers spaced in intervals on a front of a silicon wafer; excavating a plurality of grooves on the front of the silicon wafer to separate the plurality of semiconductor device layers; filling each of the plurality of grooves with each of a plurality of first spacer materials; grinding a back of the silicon wafer until the first spacer materials being exposed; attaching a plurality of metal layers to a region of the back of the silicon wafer opposite to the plurality of semiconductor device layers; and electrically connecting each of independent plurality of lead frames to the plurality of metal layers respectively. The present invention further includes the structure of the power device.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first liner on the MTJ; forming a second liner on the first liner; forming an inter-metal dielectric (IMD) layer on the MTJ, and forming a metal interconnection in the IMD layer, the second liner, and the first liner to electrically connect the MTJ. Preferably, the first liner and the second liner are made of different materials.

Abstract: A magnetoresistive random access memory (MRAM), including multiple cell array regions, multiple MRAM cells disposed in the cell array region, a silicon nitride liner conformally covering on the MRAM cells, an atomic layer deposition dielectric layer covering on the silicon nitride liner in the cell array region, wherein the surface of atomic layer deposition dielectric layer is a curved surface concave downward to the silicon nitride liner at the boundary of MRAM cells, and an ultra low-k dielectric layer covering on the atomic layer deposition dielectric layer.

Abstract: A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor.