Patents by Inventor Yi-Hung Chen
Yi-Hung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11177308Abstract: CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a plurality of dielectric patterns, a first conductive element and a second conductive element. The semiconductor substrate has a pixel region and a circuit region. The dielectric patterns are disposed between the first portion and the second portion, wherein top surfaces of the plurality of dielectric patterns are lower than top surfaces of the first and second portions. The first conductive element is disposed below the plurality of dielectric patterns. The second conductive element inserts between the plurality of dielectric patterns to electrically connect the first conductive element.Type: GrantFiled: May 6, 2019Date of Patent: November 16, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chien Ku, Huai-Jen Tung, Keng-Ying Liao, Yi-Hung Chen, Shih-Hsun Hsu, Yi-Fang Yang
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Publication number: 20210304359Abstract: The present disclosure describes systems and techniques for creating a super-resolution image (122) of a scene captured by a user device (102). Natural handheld motion (110) introduces, across multiple frames (204, 206, 208) of an image of a scene, sub-pixel offsets that enable the use of super-resolution computations (210) to form color planes (212, 214, 216), which are accumulated (218) and combined (220) to create a super-resolution image (122) of the scene.Type: ApplicationFiled: August 6, 2019Publication date: September 30, 2021Applicant: Google LLCInventors: Yi Hung Chen, Chia-Kai Liang, Bartlomiej Maciej Wronski, Peyman Milanfar, Ignacio Garcia Dorado
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Patent number: 11132031Abstract: An electronic device including a first body, a second body, a hinge structure, an electronic assembly and a linkage mechanism is provided. The first body and the second body are pivoted to each other through the hinge structure. The electronic assembly is disposed on the first body. The linkage mechanism is disposed in the first body and connected between the hinge structure and the electronic assembly. When the second body is closed to the first body, the electronic assembly is hidden between the first body and the second body. When the second body is opened relative to the first body with an opening angle less than a predetermined angle, the hinge structure does not drive the linkage mechanism. When the second body is opened relative to the first body with the opening angle not less than the predetermined angle, the hinge structure drives the linkage mechanism and the linkage mechanism drives the electronic assembly to be opened relative to the first body.Type: GrantFiled: July 7, 2020Date of Patent: September 28, 2021Assignee: COMPAL ELECTRONICS, INC.Inventors: Che-Hsien Lin, Che-Hsien Chu, Ko-Yen Lu, Chun-Chieh Chen, Chen-Ming Lee, Yi-Hung Chen, I-Chien Huang
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Patent number: 11098955Abstract: A micro-scale wireless heater includes: a support layer having first and second sides and a cavity formed on the second side; a first electrode plate and a first conduction line disposed on the second side; a second electrode plate and a coil both embedded into a slot on the first side, wherein the support layer is disposed between the first and second electrode plates forming a capacitor, the coil forms an inductor, and the slot communicates with the cavity; and a second conduction line disposed in the cavity. The first and second electrode plates are electrically connected together through the first and second conduction lines and the coil in order. Three exposed surfaces of the second electrode plate, the coil and the first side are flush with one another. The inductor and the capacitor convert an electromagnetic wave into heat. A fabrication method and applications thereof are also provided.Type: GrantFiled: January 24, 2019Date of Patent: August 24, 2021Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Hung-Yin Tsai, Tung Che Lee, Ping Huan Tsai, Shang Ru Wu, Yi Hung Chen
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Publication number: 20210011525Abstract: An electronic device including a first body, a second body, a hinge structure, an electronic assembly and a linkage mechanism is provided. The first body and the second body are pivoted to each other through the hinge structure. The electronic assembly is disposed on the first body. The linkage mechanism is disposed in the first body and connected between the hinge structure and the electronic assembly. When the second body is closed to the first body, the electronic assembly is hidden between the first body and the second body. When the second body is opened relative to the first body with an opening angle less than a predetermined angle, the hinge structure does not drive the linkage mechanism. When the second body is opened relative to the first body with the opening angle not less than the predetermined angle, the hinge structure drives the linkage mechanism and the linkage mechanism drives the electronic assembly to be opened relative to the first body.Type: ApplicationFiled: July 7, 2020Publication date: January 14, 2021Applicant: COMPAL ELECTRONICS, INC.Inventors: Che-Hsien Lin, Che-Hsien Chu, Ko-Yen Lu, Chun-Chieh Chen, Chen-Ming Lee, Yi-Hung Chen, I-Chien Huang
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Patent number: 10811423Abstract: The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.Type: GrantFiled: November 30, 2018Date of Patent: October 20, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Keng-Ying Liao, Po-Zen Chen, Yi-Jie Chen, Yi-Hung Chen
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Patent number: 10665466Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask.Type: GrantFiled: December 13, 2018Date of Patent: May 26, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Keng-Ying Liao, Chung-Bin Tseng, Po-Zen Chen, Yi-Hung Chen, Yi-Jie Chen
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Publication number: 20200158442Abstract: A micro-scale wireless heater includes: a support layer having first and second sides and a cavity formed on the second side; a first electrode plate and a first conduction line disposed on the second side; a second electrode plate and a coil both embedded into a slot on the first side, wherein the support layer is disposed between the first and second electrode plates forming a capacitor, the coil forms an inductor, and the slot communicates with the cavity; and a second conduction line disposed in the cavity. The first and second electrode plates are electrically connected together through the first and second conduction lines and the coil in order. Three exposed surfaces of the second electrode plate, the coil and the first side are flush with one another. The inductor and the capacitor convert an electromagnetic wave into heat. A fabrication method and applications thereof are also provided.Type: ApplicationFiled: January 24, 2019Publication date: May 21, 2020Inventors: Hung-Yin TSAI, Tung Che LEE, Ping Huan TSAI, Shang Ru WU, Yi Hung CHEN
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Patent number: 10522585Abstract: A semiconductor device includes a substrate, a conductive layer, a transparent layer, a transparent hard mask layer, a carrier, and a device layer. The substrate has a first surface and a second surface opposite to each other. The conductive layer is disposed on the first surface of the substrate. The transparent layer is disposed on the conductive layer. The transparent hard mask layer is disposed on the transparent layer, in which the substrate has an etch selectivity with respect to the transparent hard mask layer. The device layer is disposed between the carrier and the second surface of the substrate, in which various portions of the device layer are respectively exposed by various through holes which pass through the transparent hard mask layer, the transparent layer, the conductive layer, and the substrate.Type: GrantFiled: April 17, 2017Date of Patent: December 31, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Fang Yang, Yi-Hung Chen, Keng-Ying Liao, Yi-Jie Chen, Shih-Hsun Hsu, Chun-Chi Lee
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Patent number: 10515939Abstract: A wafer-level package includes a plurality of dies and a plurality of connection paths. The dies include at least a first die and a second die. The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output (I/O) pads arranged on the first side of the first die to I/O pads arranged on the first side of the second die, wherein adjacent I/O pads on the first side of the first die are connected to adjacent I/O pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.Type: GrantFiled: February 3, 2016Date of Patent: December 24, 2019Assignee: MEDIATEK INC.Inventors: Yi-Hung Chen, Yuan-Chin Liu
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Publication number: 20190259800Abstract: CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a plurality of dielectric patterns, a first conductive element and a second conductive element. The semiconductor substrate has a pixel region and a circuit region. The dielectric patterns are disposed between the first portion and the second portion, wherein top surfaces of the plurality of dielectric patterns are lower than top surfaces of the first and second portions. The first conductive element is disposed below the plurality of dielectric patterns. The second conductive element inserts between the plurality of dielectric patterns to electrically connect the first conductive element.Type: ApplicationFiled: May 6, 2019Publication date: August 22, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chien Ku, Huai-Jen Tung, Keng-Ying Liao, Yi-Hung Chen, Shih-Hsun Hsu, Yi-Fang Yang
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Publication number: 20190140010Abstract: CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a dielectric layer, an interconnect, a bonding pad and a dummy pattern. The semiconductor substrate has a pixel region and a circuit region. The dielectric layer is surrounded by the semiconductor substrate in the circuit region. The interconnect is disposed over the dielectric layer in the circuit region. The bonding pad is disposed in the dielectric layer and electrically connects the interconnect in the circuit region. The dummy pattern is disposed in the dielectric layer and surrounds the bonding pad in the circuit region.Type: ApplicationFiled: January 31, 2018Publication date: May 9, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chien Ku, Huai-Jen Tung, Keng-Ying Liao, Yi-Hung Chen, Shih-Hsun Hsu, Yi-Fang Yang
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Patent number: 10283548Abstract: CMOS sensors and methods of forming the same are disclosed. The CMOS sensor includes a semiconductor substrate, a dielectric layer, an interconnect, a bonding pad and a dummy pattern. The semiconductor substrate has a pixel region and a circuit region. The dielectric layer is surrounded by the semiconductor substrate in the circuit region. The interconnect is disposed over the dielectric layer in the circuit region. The bonding pad is disposed in the dielectric layer and electrically connects the interconnect in the circuit region. The dummy pattern is disposed in the dielectric layer and surrounds the bonding pad in the circuit region.Type: GrantFiled: January 31, 2018Date of Patent: May 7, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chien Ku, Huai-Jen Tung, Keng-Ying Liao, Yi-Hung Chen, Shih-Hsun Hsu, Yi-Fang Yang
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Patent number: 10269814Abstract: The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.Type: GrantFiled: April 20, 2016Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Keng-Ying Liao, Po-Zen Chen, Yi-Jie Chen, Yi-Hung Chen
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Publication number: 20190115222Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask.Type: ApplicationFiled: December 13, 2018Publication date: April 18, 2019Inventors: Keng-Ying LIAO, Chung-Bin TSENG, Po-Zen CHEN, Yi-Hung CHEN, Yi-Jie CHEN
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Patent number: 10261928Abstract: A wafer-level package includes a first die and a second die that are wafer-level packaged. The first die has a first clock source. The second die has a second clock source. The first clock source generates a clock shared by the first die and the second die. The second clock source, however, does not generate a clock used by any of the first die and the second die.Type: GrantFiled: June 26, 2018Date of Patent: April 16, 2019Assignee: Nephos (Hefei) Co. Ltd.Inventors: Yi-Hung Chen, Yuan-Chin Liu
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Publication number: 20190109147Abstract: The present disclosure provides a method of fabricating a semiconductor structure, and the method includes following steps. A gate structure is formed on a substrate, and a liner layer is formed to cover the gate structure and the substrate. A spacer layer is formed on the liner layer, and an etching gas is continuously provided to remove a portion of the spacer layer while maintaining the substrate at a second pressure, which the etching gas has a first pressure. The second pressure is greater than the first pressure.Type: ApplicationFiled: November 30, 2018Publication date: April 11, 2019Inventors: Keng-Ying LIAO, Po-Zen Chen, Yi-Jie Chen, Yi-Hung Chen
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Patent number: 10163646Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes forming a film over a substrate. The semiconductor device structure includes forming a first mask layer over the film. The semiconductor device structure includes forming a second mask layer over the first mask layer. The second mask layer exposes a first portion of the first mask layer. The semiconductor device structure includes performing a plasma etching and deposition process to remove the first portion of the first mask layer and to form a protection layer over a first sidewall of the second mask layer. The first mask layer exposes a second portion of the film after the plasma etching and deposition process. The semiconductor device structure includes removing the second portion using the first mask layer and the second mask layer as an etching mask.Type: GrantFiled: February 27, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Keng-Ying Liao, Chung-Bin Tseng, Po-Zen Chen, Yi-Hung Chen, Yi-Jie Chen
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Patent number: 10141362Abstract: A semiconductor device having a protection layer wrapping around a conductive structure is provided. The semiconductor device comprises an image sensor device layer, an interconnect layer over the image sensor device layer, a first bonding layer over the interconnect layer, a second bonding layer bonded with the first bonding layer, a substrate over the second bonding layer, and a conductive via passing through the substrate, the second bonding layer, and the first bonding layer. The conductive via comprises a protection layer and a conductive material. The protection layer is peripherally enclosed by the substrate, the second bonding layer, and the first bonding layer. The protection layer covers a sidewall cut formed at an interface of the second bonding layer and the first bonding layer. The conductive material is peripherally enclosed by the protection layer.Type: GrantFiled: March 12, 2018Date of Patent: November 27, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Wei Sung, Yi-Hung Chen, Keng-Ying Liao, Yi-Fang Yang, Chih-Yu Wu
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Publication number: 20180315790Abstract: A semiconductor device having a protection layer wrapping around a conductive structure is provided. The semiconductor device comprises an image sensor device layer, an interconnect layer over the image sensor device layer, a first bonding layer over the interconnect layer, a second bonding layer bonded with the first bonding layer, a substrate over the second bonding layer, and a conductive via passing through the substrate, the second bonding layer, and the first bonding layer. The conductive via comprises a protection layer and a conductive material. The protection layer is peripherally enclosed by the substrate, the second bonding layer, and the first bonding layer. The protection layer covers a sidewall cut formed at an interface of the second bonding layer and the first bonding layer. The conductive material is peripherally enclosed by the protection layer.Type: ApplicationFiled: March 12, 2018Publication date: November 1, 2018Inventors: Chih-Wei Sung, Yi-Hung Chen, Keng-Ying Liao, Yi-Fang Yang, Chih-Yu Wu