Patents by Inventor Yi-Hung Lin

Yi-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160290013
    Abstract: A lockable tool box contains: a base, a top cover, a connection unit, and a locking unit. The connection unit is in connection with a first side of the base and a first side of the top cover. The locking unit includes a first fixing member, a second fixing member, a rotating seat, a movable cap, and a lock button. The first fixing member has an engaging slot and a retaining slot, wherein the retaining slot has a through orifice and a stop cliff; the second fixing member extends outwardly from the base, and the rotating seat is coupled with the second fixing member and is joined with the movable cap. The movable cap has an affix block and a trench, the lock button is slidably retained in the trench of and is moved between a locking position and an unlocking position, wherein the lock button has a protrusion.
    Type: Application
    Filed: April 2, 2015
    Publication date: October 6, 2016
    Inventor: Yi-Hung LIN
  • Publication number: 20160252565
    Abstract: An example semiconductor wafer includes a semiconductor layer, a dielectric layer disposed on the semiconductor layer, and a layer of the metal disposed on the dielectric layer. An example method of determining an effective work function of a metal on the semiconductor wafer includes determining a surface barrier voltage of the semiconductor wafer, and determining a metal effective work function of the semiconductor wafer based, at least in part, on the surface barrier voltage.
    Type: Application
    Filed: February 26, 2016
    Publication date: September 1, 2016
    Inventors: Dmitriy Marinskiy, Thye Chong Loy, Jacek Lagowski, Sung-Li Wang, Lin-Jung Wu, Shyh-Shin Ferng, Yi-Hung Lin, Sheng-Shin Lin
  • Patent number: 9425287
    Abstract: A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (E/G) ratio of process gases used in the first growth stage; and performing a second growth stage with a second E/G ratio of process gases used in the second growth stage different from the first E/G ratio.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Cheng, Yi-Hung Lin, Tze-Liang Lee, Chii-Horng Li
  • Patent number: 9412868
    Abstract: A method for fabricating a semiconductor device includes forming an isolation feature in a substrate, forming a gate stack over the substrate, forming a source/drain (S/D) recess cavity in the substrate, where the S/D recess cavity is positioned between the gate stack and the isolation feature. The method further includes forming an epitaxial (epi) material in the S/D recess cavity, where the epi material has an upper surface which including a first crystal plane. Additionally, the method includes performing a redistribution process to the epi material in the S/D recess cavity using a chlorine-containing gas, where the first crystal plane is transformed to a second crystal plane after the redistribution.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: August 9, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Ru Lee, Ming-Hua Yu, Tze-Liang Lee, Chii-Horng Li, Pang-Yen Tsai, Lilly Su, Yi-Hung Lin, Yu-Hung Cheng
  • Patent number: 9398926
    Abstract: An interspinous stabilization device includes: (1) a supporting member with a top surface and a bottom surface both being configured to engage spinous processes; (2) two side members connected to the supporting member; (3) a fastener attached to the side members; and optionally (4) two extendable arms each secured on one of the side members.
    Type: Grant
    Filed: May 5, 2009
    Date of Patent: July 26, 2016
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Shi Weng, Yi-Hung Lin, Ya-Jen Yu, Shan-Chang Chueh, I-Ching Wu, Chris I. Huang
  • Patent number: 9375835
    Abstract: A tool box assembly contains plural tool boxes with a same size or different sizes, and each tool box has a first casing and a second casing. The first casing includes at least one groove defined on a top thereof, and the first casing also includes at least one engaging portion arranged on a peripheral side of the at least one groove. The second casing covers with the first casing and includes at least one protrusion mounted on a bottom thereof and corresponding to the at least one groove of the first casing. In addition, each of the at least one protrusion has a joining portion arranged on a peripheral wall thereof and corresponding to each of the at least one engaging portion of the first casing. Thereby, the plural tool boxes with the same size or the different sizes are stacked and fixed together easily and securely.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: June 28, 2016
    Assignee: FAIRNESS TECHNOLOGY CORP.
    Inventor: Yi-Hung Lin
  • Publication number: 20160126105
    Abstract: A method embodiment for forming a semiconductor device includes providing a dielectric layer having a damaged surface and repairing the damaged surface of the dielectric layer. Repairing the damaged surface includes exposing the damaged surface of the dielectric layer to a precursor chemical, activating the precursor chemical using light energy, and filtering out a spectrum of the light energy while activating the precursor chemical.
    Type: Application
    Filed: October 30, 2014
    Publication date: May 5, 2016
    Inventors: Yi-Hung Lin, Sheng-Shin Lin, Ying-Chieh Hung, Yu-Ting Huang, Tze-Liang Lee
  • Publication number: 20160064268
    Abstract: A substrate-retaining device with improved thermal uniformity is provided. In an exemplary embodiment, the substrate-retaining device includes a substantially circular first surface with a defined perimeter, a plurality of contact regions disposed at the perimeter, and a plurality of noncontact regions also disposed at the perimeter. The contact regions are interspersed with the noncontact regions. Within each of the noncontact regions, the first surface extends past where the first surface ends within each of the contact regions. In some such embodiments, each region of the plurality of contact regions includes a contact surface disposed above the first surface.
    Type: Application
    Filed: August 28, 2014
    Publication date: March 3, 2016
    Inventors: Yi-Hung Lin, Jr-Hung Li, Chang-Shen Lu, Tze-Liang Lee, Chii-Horng Li
  • Patent number: 9252297
    Abstract: An optoelectronic device comprises an optoelectronic semiconductor stack layer; a conductive layer on the optoelectronic semiconductor stack layer, the conductive layer comprising a top surface, a bottom surface opposite to the top surface, and a side surface; a first barrier layer covering the top surface; a second barrier layer covering the bottom surface; and a first metal oxide layer, wherein the first metal oxide layer covers the side surface, the first barrier layer, and the second barrier layer.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: February 2, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Yi-Hung Lin, Cheng-Hong Chen
  • Publication number: 20150296564
    Abstract: An apparatus, a system and a method are disclosed. An exemplary method includes providing a wafer process chamber and a plurality of radiant heat elements under the wafer process chamber, receiving a wafer holder configured to be used in the wafer process chamber, and processing a wafer located on the wafer holder in the wafer process chamber. The wafer holder includes: a wafer contact portion including an upper surface and a lower surface, an exterior portion including an upper surface and a lower surface, and a tapered region formed in the wafer contact portion.
    Type: Application
    Filed: June 25, 2015
    Publication date: October 15, 2015
    Inventors: Yi-Hung Lin, Li-Ting Wang, Tze-Liang Lee
  • Patent number: 9153944
    Abstract: A light-emitting array comprises a plurality of light-emitting elements, wherein each of the plurality of light-emitting elements comprises a first semiconductor stack; and a plurality of bridge structures connected to the plurality of light-emitting elements, wherein the plurality of light-emitting elements are spaced apart by the plurality of bridge structures, wherein each of the plurality of bridge structures comprise a second semiconductor stack which has the same epitaxial stack as the first semiconductor stack.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: October 6, 2015
    Assignee: EPISTAR CORPORATION
    Inventors: Shih-Chang Lee, Chih-Chiang Lu, Yi-Hung Lin, Wu-Tsung Lo, Ta-Chuan Kuo
  • Publication number: 20150279632
    Abstract: A device includes a pedestal. The pedestal includes a ground electrode, a central portion, and a peripheral portion. The ground electrode includes a top surface from which the peripheral portion is projected, thereby having a height difference between the central portion and the peripheral portion.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 1, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: KUN-MO LIN, KEITH KUANG-KUO KOAI, CHIH-TSUNG LEE, VICTOR Y. LU, YI-HUNG LIN
  • Publication number: 20150273794
    Abstract: A prepreg element with improved structure comprises at least two layers of filament sheet that are stacked on top of each other, wherein each layer of filament sheet is filled with materials having a linear pattern in a unitary orientation in horizontal plane, and is further coated with resin on its surface; when stacked up, two layers of filament sheet that are adjacent to each other have the linear patterns in different orientations; the at least two layers of filament sheet with different orientations is subsequently processed through coating, yarn expanding and laminating to provide tensile strength in multiple orientations in horizontal plane, and increase the overall structural strength with no extra thickness being added to the material, nor is added to overall appearance of the prepreg element, so as to achieve the improvement of structural strength and toughness without adding extra thickness.
    Type: Application
    Filed: January 10, 2015
    Publication date: October 1, 2015
    Inventors: CHIH-HSIAO CHIEN, YI-HUNG LIN
  • Patent number: 9138883
    Abstract: A tool box of the present invention comprises a tool handle, a case, and cap. The tool handle comprises a housing, a battery assembly, a luminous source, and a conductive element. The luminous source comprises a first leg and a second leg. One of the anode and the cathode electrically connects to the first leg. A top surface of the cap is formed with an engaging groove. The housing of the tool handle engages in the engaging groove. Wherein either the other one of the anode and the cathode or the second leg electrically connects to the conductive element when a tool inserts to the housing and pushes the conductive element to move to the second position. As such, the tool handle can turn on and off the luminous without disposing any switch. An interior of the case has enough space for receiving tools.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: September 22, 2015
    Inventor: Yi-Hung Lin
  • Patent number: 9123634
    Abstract: Disclosed is a method for yield enhancement of making a semiconductor device. The method for yield enhancement of making a semiconductor device comprises the steps of: providing the semiconductor device comprising an epitaxial layer including a defect; forming a dielectric layer on the epitaxial layer; detecting and identifying a location of the defect; and etching the dielectric layer and leaving a part of the dielectric layer to cover an area substantially corresponding to the detected defect. The semiconductor device made by the method is also disclosed.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: September 1, 2015
    Assignee: EPISTAR CORPORATION
    Inventors: Yi Hung Lin, Yu Chih Yang, Wu Tsung Lo
  • Publication number: 20150222094
    Abstract: A light-emitting array comprises a plurality of light-emitting elements, wherein each of the plurality of light-emitting elements comprises a first semiconductor stack; and a plurality of bridge structures connected to the plurality of light-emitting elements, wherein the plurality of light-emitting elements are spaced apart by the plurality of bridge structures, wherein each of the plurality of bridge structures comprise a second semiconductor stack which has the same epitaxial stack as the first semiconductor stack.
    Type: Application
    Filed: February 5, 2014
    Publication date: August 6, 2015
    Applicant: Epistar Corporation
    Inventors: Shih-Chang LEE, Chih-Chiang LU, Yi-Hung LIN, Wu-Tsung LO, Ta-Chuan KUO
  • Patent number: 9099514
    Abstract: An apparatus, a system and a method are disclosed. An exemplary apparatus includes a wafer holder including a first portion and a second portion. The first and second portions are formed of the same continuous material. The first portion includes a first upper surface and a first lower surface, and the second portion including a second upper surface and a second lower surface. The apparatus further includes an interface between the first and second portions. The interface provides for a transition such that the first upper surface of the first portion tends toward the second upper surface of the second portion. The apparatus further includes a tapered region formed in the first portion. The tapered region starts at a radial distance from a center line of the wafer holder and terminates at the interface. The tapered region has an initial thickness that gradually decreases to a final thickness.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: August 4, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hung Lin, Li-Ting Wang, Tze-Liang Lee
  • Publication number: 20150191820
    Abstract: An injector for forming films respectively on a stack of wafers is provided. The injector includes a plurality of hole structures. Every adjacent two of the wafers have therebetween a wafer spacing, and each of the wafers has a working surface. The hole structures respectively correspond to the respective wafer spacings. The working surface and a respective hole structure have therebetween a parallel distance. The parallel distance is larger than a half of the wafer spacing. A wafer processing apparatus and a method for forming films respectively on a stack of wafers are also provided.
    Type: Application
    Filed: March 23, 2015
    Publication date: July 9, 2015
    Inventors: WEI-CHE HSIEH, BRIAN WANG, TZE-LIANG LEE, YI-HUNG LIN, HAO-MING LIEN, SHIANG-RUNG TSAI, TAI-CHUN HUANG
  • Publication number: 20150150557
    Abstract: A bionic fixing apparatus is provided. The bionic fixing apparatus includes a body having a through hole and at least one slit. The through hole penetrates the body from the top surface to the bottom surface to form a top opening and a bottom opening. An inner diameter of the top opening is larger than an inner diameter of the bottom opening. The slit is connected to the bottom opening and extends upwardly from the bottom surface of the body, such that the body has a flexible bottom portion.
    Type: Application
    Filed: November 26, 2014
    Publication date: June 4, 2015
    Applicants: NATIONAL TAIWAN UNIVERSITY HOSPITAL, INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Pei-Yi TSAI, Chih-Chieh HUANG, Yi-Hung WEN, Hsin-Hsin SHEN, Yi-Hung LIN, De-Yau LIN, Jui-Sheng SUN, Chuan-Sheng CHUANG, An-Li CHEN, Ching-Chih LIN
  • Patent number: D735995
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: August 11, 2015
    Assignee: FAIRNESS TECHNOLOGY CORP.
    Inventor: Yi-Hung Lin