Abstract: A method and structure providing an optical sensor having an optimized Ge—Si interface includes providing a substrate having a pixel region and a logic region. In some embodiments, the method further includes forming a trench within the pixel region. In various examples, and after forming the trench, the method further includes forming a doped semiconductor layer along sidewalls and along a bottom surface of the trench. In some embodiments, the method further includes forming a germanium layer within the trench and over the doped semiconductor layer. In some examples, and after forming the germanium layer, the method further includes forming an optical sensor within the germanium layer.

Abstract: A memory device may be provided, including a base layer; an insulating layer arranged over the base layer, where the insulating layer may include a recess having opposing side walls; a first electrode arranged along the opposing side walls of the recess; a switching element arranged along the first electrode; a second electrode arranged along the switching element; and a capping layer arranged over the recess, where the capping layer may at least partially overlap the first electrode, the switching element and the second electrode.

Abstract: A compilation method includes obtaining a source program code. The source program code includes a first function in a first language code and a second function in a second language code. The first language code is a native language. The second language code is a non-native language. The method also includes generating a third language code based on the source program code. The third language code includes a third function, a fourth function and a fifth function. The third function is generated based on the first function. The fourth function is generated based on the second function. The fifth function is generated based on the first function and the second function. Executing the third function invokes the fourth function via the fifth function.

Abstract: A semiconductor device may be provided, including a base layer, an insulating layer arranged over the base layer, a memory structure arranged at least partially within the insulating layer, where the memory structure may include a first electrode, a second electrode, and an intermediate element between the first electrode and the second electrode, and a resistor arranged at least partially within the insulating layer, where the resistor may be arranged in substantially a same horizontal plane with one of the first electrode and the second electrode.

Abstract: Embodiments of the present disclosure relate to a method, device and computer program product for software bug verification. In one embodiment, the method includes determining a test action for verification of a software bug to be verified based on an identification of the software bug. The method further includes determining similarities between the test action and a plurality of historical test actions. The method further includes in response to a similarity between the test action and at least one of the plurality of historical test actions exceeding a threshold similarity, associating the test action with a code fragment category associated with the at least one historical test action. The method further includes verifying the software bug by running one code fragment in the code fragment category.

Abstract: A memory device may be provided, including a base layer; an insulating layer arranged over the base layer, where the insulating layer may include a recess having opposing side walls; a first electrode arranged along the opposing side walls of the recess; a switching element arranged along the first electrode; a second electrode arranged along the switching element; and a capping layer arranged over the recess, where the capping layer may at least partially overlap the first electrode, the switching element and the second electrode.

Abstract: An electronic device such as a wristwatch may have a housing with metal portions such as metal sidewalls. The housing may form an antenna ground for an antenna. An antenna resonating element for the antenna may be formed from a stack of capacitively coupled component layers such as a display layer, touch sensor layer, and near-field communications antenna layer at a front face of the device. An additional antenna may be formed from a peripheral resonating element that runs along a peripheral edge of the device and the antenna ground. A rear face antenna may be formed using a wireless power receiving coil as a radio-frequency antenna resonating element or may be formed from metal antenna traces on a plastic support for light-based components.

Abstract: An electronic device may be provided with wireless communications circuitry and control circuitry. The wireless communications circuitry may include centimeter and millimeter wave transceiver circuitry and a phased antenna array. A dielectric cover may be formed over the phased antenna array. The phased antenna array may transmit and receive wireless radio-frequency signals through the dielectric cover. The dielectric cover may have first and second opposing surfaces. The second surface may face the phased antenna array and may have a curvature. The curvature of the second surface may include one or more recessed regions of the dielectric cover. The one or more recessed regions of the second surface may serve to maximize and broaden the coverage area for the phased antenna array. The first surface may be conformal to other structures in the electronic device.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.

Abstract: A drilling system including a feed control module, a force control module, a hole breaking control module, a conversion module and a computing unit is provided. The feed control module sets a feed force threshold and a feed speed threshold for the computing unit to determine whether the current mode satisfies a first conversion condition. The hole breaking control module sets a drilling penetration force threshold and a drilling penetration speed threshold for the computing unit to determine whether the current mode satisfies a second conversion condition. The conversion module informs to change the feed force and the feed speed according to the determination results of the two conversion conditions. The force control module provides the feed force. With the drilling system, possible impact on the workpiece due to resistance change which occurs when the drill just touches and nearly gets through the workpiece will be reduced.

Abstract: The present invention discloses a system and control method of all-DC power supply and storage for a building. The system includes a renewable energy power generation apparatus, a mains grid system, a first DC/DC conversion apparatus, an AC/DC conversion apparatus, a first voltage DC bus, a first energy storage apparatus, and a first charge-discharge conversion apparatus. The first DC/DC conversion apparatus is configured to convert DC voltage generated by the renewable energy power generation apparatus to voltage of the first voltage DC bus. The AC/DC conversion apparatus is configured to convert AC power from the mains grid system to DC power. The first charge-discharge conversion apparatus is configured to control charge/discharge of the first energy storage apparatus. The first voltage DC bus is connected to a first electrical device and configured to power the first electrical device.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure including a switching element arranged between a pair of conductors, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure includes a switching element arranged between a pair of conductors, in which the switching element of the reference cell structure has a dimension that is different from a dimension of the switching element of the main cell structure.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including an opening in a dielectric structure, the opening having a sidewall, a first electrode on the sidewall of the opening, a spacer layer on the first electrode, a resistive layer on the first electrode and upon an upper surface of the spacer layer, and a second electrode on the resistive layer.

Abstract: An electronic device may be provided with a dielectric cover and a phased antenna array for conveying millimeter wave signals. A conductive pocket may be mounted to the cover. The pocket may include a conductive rear wall and conductive sidewalls that extend from a periphery of the rear wall to the cover. The array may be mounted to the rear wall and may convey signals through the cover. The sidewalls may extend from the cover at non-zero angles with respect to the normal axis of the cover. The shape of the pocket and the cover may be selected so that the pocket is non-resonant at frequencies handled by the array, to mitigate destructive interference within the pocket, to block surface waves from propagating along the cover, and to tweak the radiation pattern of the array to exhibit a desired shape and directionality.

Abstract: A head-mounted device may have a head-mounted housing. The housing may include a frame with left and right openings that receive respective left and right optical modules that present images to a user's eyes. Each optical module may have a lens and display that presents an image through the lens. Camera support members may be coupled to respective left and right peripheral portions of the frame. Each camera support member may have openings configured to receive cameras. Antennas may be formed on a camera support member. The antennas may have metal traces on a surface of the camera support member, may have conductive structures embedded within the camera support member, and/or may have patterned metal traces on printed circuits attached to or embedded in the camera support member. The cameras may operate through portions of a display cover layer that covers an outwardly-facing display on the head-mounted housing.

Abstract: An electronic device may include a curved cover layer and an antenna. The antenna may include a ground and a resonating element on a curved surface of a substrate. The curved surface may have a curvature that matches that of the cover layer. The resonating element may include first, second, and third arms fed by a feed. The first arm and a portion of the ground may form a loop antenna resonating element. The second arm and the first arm may form an inverted-F antenna resonating element, where a portion of the first arm forms a return path to the antenna ground for the inverted-F antenna resonating element. A gap between the first and second arms may form a distributed capacitance. The third arm may form an L-shaped antenna resonating element. The antenna may have a wide bandwidth from below 2.4 GHz to greater than 9.0 GHz.

Abstract: An electronic device may be provided with wireless circuitry. The wireless circuitry may include one or more antennas. The antennas may include phased antenna arrays each of which includes multiple antenna elements. Phased antenna arrays may be mounted along edges of a housing for the electronic device, behind a dielectric window such as a dielectric logo window in the housing, in alignment with dielectric housing portions at corners of the housing, or elsewhere in the electronic device. A phased antenna array may include arrays of patch antenna elements on dielectric layers separated by a ground layer. A baseband processor may distribute wireless signals to the phased antenna arrays at intermediate frequencies over intermediate frequency signal paths. Transceiver circuits at the phased antenna arrays may include upconverters and downconverters coupled to the intermediate frequency signal paths.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure having a dimension, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure has a dimension that is different from the dimension of the main cell structure, in which the main cell structure and the reference cell structure include a switching element arranged between a pair of conductors.

Abstract: Integrated circuits with embedded memory structures, and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming from a first metallization layer a first lower conductive interconnect in a first region of a dielectric layer and a second lower conductive interconnect in a second region of the dielectric layer. The method includes forming a memory structure in the first region. Further, the method includes depositing an interlayer dielectric over the first region and over the second region. Also, the method includes forming from a second metallization layer a first upper conductive interconnect over the interlayer dielectric, wherein the first upper conductive interconnect is coupled to the memory structure.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure having a dimension, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure has a dimension that is different from the dimension of the main cell structure, in which the main cell structure and the reference cell structure include a switching element arranged between a pair of conductors.