Patents by Inventor Yi Jiang
Yi Jiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11922838Abstract: A display panel, comprising a first insulating structural layer, a first crack detection line, a second insulating structural layer and a second crack detection line which are sequentially arranged on a substrate, wherein the first crack detection line and the second crack detection line are both located in a peripheral area and are arranged around a display area, one end of the first crack detection line is configured to receive a detection signal, and the other end of the first crack detection line is configured to output a first output signal, and one end of the second crack detection line is configured to receive a detection signal and the other end of the second crack detection line is configured to output a second output signal.Type: GrantFiled: April 13, 2021Date of Patent: March 5, 2024Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Yu Wang, Yi Zhang, Tingliang Liu, Chang Luo, Hao Zhang, Huijuan Yang, Tinghua Shang, Yang Zhou, Pengfei Yu, Shun Zhang, Xiaofeng Jiang, Huijun Li, Linhong Han
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Patent number: 11923621Abstract: An electronic device may be provided with a phased antenna array on an antenna module. The array may include low band antennas and high band antennas that radiate at frequencies greater than 10 GHz. The module may include antenna layers, transmission line layers, and ground traces that separate the antenna layers from the transmission line layers. The low band antennas and the high band antennas may have radiators patterned onto the antenna layers. The radiators may be fed by transmission lines on the transmission line layers. The antenna layers may have a dielectric permittivity that is greater than the dielectric permittivity of the transmission line layers. This may serve to reduce the lateral footprint of the low band and high band antennas, which allows the antennas to be interleaved along a common linear axis in the phased antenna array, thereby minimizing the lateral footprint of the antenna module.Type: GrantFiled: June 3, 2021Date of Patent: March 5, 2024Assignee: Apple Inc.Inventors: Jiangfeng Wu, Siwen Yong, Simon G. Begashaw, Yi Jiang, Lijun Zhang
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Patent number: 11906867Abstract: An electrochemical device is disclosed. The electrochemical device includes a first transparent conductive layer, an electrochromic layer overlying the first transparent conductive layer, a counter electrode layer overlying the electrochromic layer, a second transparent conductive layer, and a switching speed parameter of not greater than 0.68 s/mm at 23° C.Type: GrantFiled: January 7, 2022Date of Patent: February 20, 2024Assignee: SAGE ELECTROCHROMICS, INC.Inventors: Hannah Leung Ray, Ruth Anne Sarah Schlitz, Yi Jiang, Camille Mesnager, Wen Li, Carlijn L. Mulder, Jean-Christophe Giron
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Patent number: 11904482Abstract: A mechanical arm calibration system and a mechanical arm calibration method are provided. The method includes: locating a position of an end point of a mechanical arm in a three-dimensional space to calculate an actual motion trajectory of the end point when the mechanical arm is operating; retrieving link parameters of the mechanical arm, randomly generating sets of particles including compensation amounts for the link parameters through particle swarm optimization (PSO), importing the compensation amounts of each of the sets of particles into forward kinematics after addition of the corresponding link parameters, to calculate an adaptive motion trajectory of the end point; calculating position errors between the adaptive motion trajectory and the actual motion trajectory of each of the sets of particles for a fitness value of the PSO to estimate a group best position; and updating the link parameters by the compensation amounts corresponding to the group best position.Type: GrantFiled: April 1, 2021Date of Patent: February 20, 2024Assignee: Industrial Technology Research InstituteInventors: Jun-Yi Jiang, Yen-Cheng Chen, Chung-Yin Chang, Guan-Wei Su, Qi-Zheng Yang
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Patent number: 11908900Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.Type: GrantFiled: July 21, 2022Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yin-Kai Liao, Sin-Yi Jiang, Hsiang-Lin Chen, Yi-Shin Chu, Po-Chun Liu, Kuan-Chieh Huang, Jyh-Ming Hung, Jen-Cheng Liu
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Patent number: 11901393Abstract: The present disclosure provides a semiconductor structure, including a substrate including a first material, wherein the first material generates electrical signals from radiation within a first range of wavelengths, an image sensor element including a second material, wherein the second material generates electrical signals from radiation within a second range of wavelengths, the second range is different from first range, a transparent layer proximal to a light receiving surface of the image sensor element, wherein the transparent layer is transparent to radiation within the second range of wavelength, and an interconnect structure connected to a signal transmitting surface of the image sensor element.Type: GrantFiled: February 25, 2021Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jhy-Jyi Sze, Sin-Yi Jiang, Yi-Shin Chu, Yin-Kai Liao, Hsiang-Lin Chen, Kuan-Chieh Huang, Jung-I Lin
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Publication number: 20240049453Abstract: A method for manufacturing a semiconductor structure includes providing a substrate; forming mutually parallel first trenches extending along a first direction in the substrate and first isolation structures filling the first trenches; forming mutually parallel second trenches extending along a second direction in the substrate and in the first isolation structures, the first and second trenches dividing the substrate to form active pillars, and a depth of the second trenches being less than that of the first trenches; forming second isolation structures alternately arranged with the first isolation structures along the second direction at bottoms of the second trenches, top surfaces of the second isolation structures being lower than bottom surfaces of the second trenches located in the first isolation structures; forming bit line structures on the second isolation structures; and forming word line structures above the bit line structures.Type: ApplicationFiled: February 17, 2023Publication date: February 8, 2024Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Guangsu SHAO, Deyuan XIAO, Yunsong QIU, YI JIANG, Xingsong SU
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Patent number: 11894608Abstract: An electronic device may have a phased antenna array. An antenna in the array may include a rectangular patch element with diagonal axes. The antenna may have first and second antenna feeds coupled to the patch element along the diagonal axes. The antenna may be rotated at a forty-five degree angle relative to other antennas in the array. The antenna may have one or two layers of parasitic elements overlapping the patch element. For example, the antenna may have a layer of coplanar parasitic patches separated by a gap. The antenna may also have an additional parasitic patch that is located farther from the patch element than the layer of coplanar parasitic patches. The additional parasitic patch may overlap the patch element and the gap in the coplanar parasitic patches. The antenna may exhibit a relatively small footprint and minimal mutual coupling with other antennas in the array.Type: GrantFiled: May 23, 2022Date of Patent: February 6, 2024Assignee: Apple Inc.Inventors: Jiangfeng Wu, Lijun Zhang, Mattia Pascolini, Siwen Yong, Yi Jiang
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Publication number: 20240008246Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base including a first region and a second region, where a plurality of active pillars are arranged at intervals in the base located in the first region; forming a first dielectric layer on the base, where the first dielectric layer covers the plurality of active pillars; forming a first mask layer with a first mask pattern on the first dielectric layer; forming a second mask layer with a second mask pattern on the first mask layer; forming a third mask layer with a third mask opening, where the third mask opening is used to expose the first region; and removing part of the first dielectric layer by using the first mask layer, the second mask layer, and the third mask layer as a mask.Type: ApplicationFiled: September 23, 2022Publication date: January 4, 2024Inventors: YI JIANG, Deyuan XIAO, Weiping BAI, Yunsong QIU, Guangsu SHAO
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Patent number: 11862838Abstract: An electronic device may include a curved cover layer and an antenna. The antenna may include a ground and a resonating element on a curved surface of a substrate. The curved surface may have a curvature that matches that of the cover layer. The resonating element may include first, second, and third arms fed by a feed. The first arm and a portion of the ground may form a loop antenna resonating element. The second arm and the first arm may form an inverted-F antenna resonating element, where a portion of the first arm forms a return path to the antenna ground for the inverted-F antenna resonating element. A gap between the first and second arms may form a distributed capacitance. The third arm may form an L-shaped antenna resonating element. The antenna may have a wide bandwidth from below 2.4 GHz to greater than 9.0 GHz.Type: GrantFiled: April 17, 2020Date of Patent: January 2, 2024Assignee: Apple Inc.Inventors: Lijun Zhang, Jiangfeng Wu, Mattia Pascolini, Siwen Yong, Yi Jiang
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Patent number: 11857024Abstract: Embodiments herein relate generally to the field of footwear, and more particularly to components of performance footwear, such as midsoles, and in particular related to a high performance composite foam for a midsole, the composite foam comprising: a pelletized expanded thermoplastic elastomer; and a polyurethane (PU) matrix, wherein the pelletized expanded thermoplastic elastomer is mixed within the PU matrix. Midsoles made from a high performance composite foam and footwear including such midsoles. A method of making a high performance midsole is also provided.Type: GrantFiled: April 16, 2019Date of Patent: January 2, 2024Assignee: COLUMBIA SPORTSWEAR NORTH AMERICA, INC.Inventors: Yi Jiang Wei, Haskell Beckham, Gary John Banik
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Patent number: 11855237Abstract: Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.Type: GrantFiled: January 9, 2023Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Jhy-Jyi Sze, Sin-Yi Jiang, Yi-Shin Chu, Yin-Kai Liao, Hsiang-Lin Chen, Kuan-Chieh Huang
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Patent number: 11854862Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base; forming a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the first trenches, wherein the initial active region includes a first initial source-drain region close to a bottom of the first trench, a second initial source-drain region away from the bottom of the first trench, and an initial channel region located between the first initial source-drain region and the second initial source-drain region; forming a protective dielectric layer, wherein the protective dielectric layer covers a sidewall of the second initial source-drain region and a sidewall of the initial channel region; thinning the first initial source-drain region.Type: GrantFiled: June 27, 2022Date of Patent: December 26, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Guangsu Shao, Deyuan Xiao, Yunsong Qiu, Youming Liu, Yi Jiang, Xingsong Su, Yuhan Zhu
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Patent number: 11848345Abstract: Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.Type: GrantFiled: February 17, 2021Date of Patent: December 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Lin Chen, Yi-Shin Chu, Yin-Kai Liao, Sin-Yi Jiang, Kuan-Chieh Huang, Jhy-Jyi Sze
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Publication number: 20230403840Abstract: Embodiments relate to a three-dimensional semiconductor structure and a formation method thereof. The three-dimensional semiconductor structure includes: a substrate; and a device structure positioned on a top surface of the substrate. The device structure includes memory rows arranged at intervals along a first direction, each of the memory rows includes memory cells arranged at intervals along a second direction and a gap between adjacent two of the memory cells, and each of the memory cells includes a first stacked layer and a word line structure. The word line structure includes a first part positioned in the first stacked layer and a second part extending out of the first stacked layer along the first direction. At least adjacent two of the memory rows exist, and the second part of the memory cell in one of the memory rows extends into the gap in another one of the memory rows.Type: ApplicationFiled: August 1, 2022Publication date: December 14, 2023Inventors: Yi JIANG, Deyuan XIAO, Youming LIU, Xingsong SU, Weiping BAI, Guangsu SHAO
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Publication number: 20230399012Abstract: A self-driving vehicle test method, apparatus, and system are provided, and relate to the field of self-driving technologies. The system includes a software control module, a motion control module, and a plurality of motion platforms. The software control module may obtain information about a first test scenario, and send the information about the first test scenario to the motion control module. After receiving the information about the first test scenario, the motion control module may determine a test motion platform and a target motion platform from the plurality of motion platforms based on the information about the first test scenario, and send parameter information of each determined motion platform to the motion platform, so that the motion platform performs a corresponding operation based on the parameter information. In this way, a self-driving vehicle can be tested without participation of test personnel, thereby improving test efficiency and reducing labor costs.Type: ApplicationFiled: April 27, 2023Publication date: December 14, 2023Inventors: Hao WU, Bende YU, Liangzhuang ZHANG, Yi JIANG
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Publication number: 20230395700Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, including a semiconductor substrate, the semiconductor substrate is provided with first trenches extending along a first direction and second trenches extending along a second direction, the first trenches intersect with the second trenches to form a plurality of semiconductor pillars on the semiconductor substrate, the second trench is filled with a first dielectric layer, a second dielectric layer is provided on a top of the semiconductor pillar, and a third dielectric layer is provided on a sidewall of the first trench; an isolation layer, located in the semiconductor substrate below the first trenches and extending along the second direction; and a bit line, located on a surface of the isolation layer and extending along the second direction, the bit line is connected to a bottom of the semiconductor pillar.Type: ApplicationFiled: September 26, 2022Publication date: December 7, 2023Inventors: Deyuan XIAO, Guangsu Shao, Yunsong Qiu, Yi Jiang, Youming Liu
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Publication number: 20230397099Abstract: A mobile network selection method, device, mobile user equipment and a storage medium are provided. The method includes when a mobile user equipment supporting a Closed Access Group CAG function automatically selects a mobile network, determining, by a Non-Access Stratum NAS function of the mobile user equipment according to information in a Universal Subscriber Identity Module USIM of the mobile user equipment, whether to allow the mobile user equipment to access a CAG cell of a Public Land Mobile Network PLMN; when the mobile user equipment receives a broadcast message of a CAG cell and the mobile user equipment is allowed to access the CAG cell of the PLMN, selecting, by the NAS function, a mobile network corresponding to a PLMN identifier indicated in the broadcast message of the CAG cell.Type: ApplicationFiled: November 5, 2021Publication date: December 7, 2023Inventors: Xu CHEN, Yi JIANG
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Publication number: 20230390364Abstract: Provided is the use of human serum albumin in the manufacturing of a drug for treating diabetes, obesity, atherosclerosis, Alzheimer's disease, Parkinson's disease and other diseases. In a preferred embodiment, the human serum albumin is the recombinantly prepared young and uninjured human serum albumin, and has achieved excellent effects in reducing the blood sugar level of a diabetic patient.Type: ApplicationFiled: November 1, 2021Publication date: December 7, 2023Applicant: Shenzhen Protgen Ltd.Inventors: Yongzhang Luo, Yan Fu, Hongyi Liu, Anji Ju, Jiaze Tang, Yi Jiang, Boyuan Ma, Xiaoqin Jiang, Yu Feng, Guodong Chang, Hui Li
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Patent number: 11835060Abstract: A range hood, includes a fan system (2), the fan system (2) having a volute (21) and an impeller (22); the volute (21) includes a front cover (211), a rear cover (212) and an annular wall (213); the annular wall (213) has a volute tongue (214); the front cover (211) has an air inlet (215), the air inlet (215) faces downward to make the range hood to be a horizontal range hood; the volute tongue (214) is gradually inclined from the rear cover (212) to the front cover (211) in a direction opposite to the rotation direction of the impeller (22).Type: GrantFiled: October 30, 2020Date of Patent: December 5, 2023Assignee: NINGBO FOTILE KITCHEN WARE CO., LTD.Inventors: Yi Jiang, Zhineng Xu, Gai Lei, Lei Shi, Wenbo Gou