Abstract: A semiconductor structure includes a plurality memory group provided in rows, each of the memory groups includes a plurality of memories arranged at intervals along a row direction, and for two adjacent ones of the memory groups, the memories in one memory group and the memories in another memory group are staggered.

Abstract: A test structure includes a plurality of word lines and a plurality of bit lines. A vertical gate-all-around (VGAA) transistor is formed at the intersection of each word line and each bit line. The test structure includes a first area and a second area. The second area is arranged outside the first area, the word lines in the first area and the word lines in the second area are disconnected, and the bit lines in the first area and the bit lines in the second area are disconnected. The plurality of VGAA transistors located in the first area form a test array, and a VGAA transistor located in the middle of the test array is a device to be tested.

Abstract: A voice information processing method and an electronic device are provided. The voice information processing method may include: a first device (1100) obtains first voice information, and when the first voice information includes a wakeup keyword, the first device (1100) sends a voice assistant wakeup instruction to a second device (1200), such that the second device (1200) launches a voice assistant; then the first device (1100) obtains second voice information and sends the second voice information to the second device (1200), the second device (1200) determines a voice triggered event corresponding to the second voice information by using the voice assistant, and feeds target information associated with performance of the voice triggered event back to the first device (1100), such that the first device (1100) performs the voice triggered event based on the target information. The method can reduce the computing burden of the first device (1100).

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate, multiple active pillars located in the substrate, and multiple word lines. The multiple active pillars are arranged in an array in a first direction and a second direction. The first direction and the second direction are both directions parallel to a top surface of the substrate, and the first direction and the second direction intersect. The multiple word lines are spaced apart in the first direction. Each of the word lines extends in the second direction and continuously surrounds and covers a portion of a side wall of each of the multiple active pillars arranged in the second direction. Any two adjacent word lines are at least partially staggered in a direction perpendicular to the top surface of the substrate.

Abstract: According to various embodiments, there is provided a memory cell. The memory cell may include a transistor, a dielectric member, an electrode and a contact member. The dielectric member may be disposed over the transistor. The electrode may be disposed over the dielectric member. The contact member has a first end and a second end opposite to the first end. The first end is disposed towards the transistor, and the second end is disposed towards the dielectric member. The contact member has a side surface extending from the first end to the second end. The second end may have a recessed end surface that has a section that slopes towards the side surface so as to form a tip with the side surface at the second end. The dielectric member may be disposed over the second end of the contact member and may include at least a portion disposed over the tip.

Abstract: Technologies are disclosed for improving the efficiency of real-time audio processing, and specifically for improving the efficiency of continuously modifying a real-time audio signal. Efficiency is improved by reducing memory bandwidth requirements and by reducing the amount of processing used to modify the real-time audio signal. In some configurations, memory bandwidth requirements are reduced by selectively transferring active samples in the frequency domain—e.g. avoiding the transfer samples with amplitudes of zero or near-zero. This has particular importance when the specialized hardware retrieves samples from main memory in real-time. In some configurations, the amount of processing needed to modify the audio signal is reduced by omitting operations that do not meaningfully affect the output audio signal. For example, a multiplication of samples may be avoided when at least one of the samples has an amplitude of zero or near-zero.

Abstract: An electronic device may have an antenna embedded in a substrate. The substrate may have first layers, second layers on the first layers, and third layers on the second layers. The antenna may include a first patch on the first layers that radiates in a first band, a second patch on the second antenna layers that radiates in a second band, and a parasitic patch on the third layers. A short path may couple ground to a location on the first patch that allows the first patch to form a ground extension in the second band for the second patch without affecting performance of the first patch in the first band. The first layers may have a higher dielectric permittivity than the second and third layers to minimize the thickness of the substrate without requiring a separate dielectric loading layer over the substrate.

Abstract: An electronic device may be provided with a phased antenna array on an antenna module. The array may include low band antennas and high band antennas that radiate at frequencies greater than 10 GHz. The module may include antenna layers, transmission line layers, and ground traces that separate the antenna layers from the transmission line layers. The low band antennas and the high band antennas may have radiators patterned onto the antenna layers. The radiators may be fed by transmission lines on the transmission line layers. The antenna layers may have a dielectric permittivity that is greater than the dielectric permittivity of the transmission line layers. This may serve to reduce the lateral footprint of the low band and high band antennas, which allows the antennas to be interleaved along a common linear axis in the phased antenna array, thereby minimizing the lateral footprint of the antenna module.

Abstract: An electronic device may have a cover layer and an antenna. A dielectric adapter may have a first surface coupled to the antenna and a second surface pressed against the cover layer. The cover layer may have a three-dimensional curvature. The second surface may have a curvature that matches the curvature of the cover layer. Biasing structures may exert a biasing force that presses the antenna against the dielectric adapter and that presses the dielectric adapter against the cover layer. The biasing force may be oriented in a direction normal to the cover layer at each point across dielectric adapter. This may serve to ensure that a uniform and reliable impedance transition is provided between the antenna and free space through the cover layer over time, thereby maximizing the efficiency of the antenna.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including an opening in a dielectric structure, the opening having a sidewall, a first electrode on the sidewall of the opening, a spacer layer on the first electrode, a resistive layer on the first electrode and upon an upper surface of the spacer layer, and a second electrode on the resistive layer.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.

Abstract: Embodiments of the present disclosure provide a method, device, and computer program product for managing a backup system. The method comprises obtaining a state of a backup system, wherein the backup system comprises a plurality of backup servers and a plurality of backup clients, the plurality of backup servers is communicatively coupled to the plurality of backup clients via a network, and wherein at least one backup server from the plurality of backup servers is configured to back up data of at least one backup client allocated from the plurality of backup clients to the at least one backup server, determining a reward score corresponding to the state of the backup system and, determining, based on the state of the backup system and the reward score, configuration information for the backup system, the configuration information indicating allocation of the plurality of backup clients to the plurality of backup servers.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material.

Abstract: An electronic device may have an antenna that conveys radio-frequency signals at frequencies greater than 10 GHz. The antenna may be embedded in a substrate. The substrate may have routing layers, first antenna layers on the routing layers, second antenna layers on the first antenna layers, and a third antenna layers on the second antenna layers. The antenna may include first traces on the first antenna layers, second traces on the second antenna layers, and third traces on the third antenna layers. The first antenna layers may have a first bulk dielectric permittivity. The second layers may have a second bulk dielectric permittivity. The third layers may have a third bulk dielectric permittivity. At least one of the first, second, and third bulk dielectric permittivities may be different from the others. This may differentially load the antenna across the antenna layers, thereby broadening the bandwidth of the antenna.

Abstract: A video tag determination method, a terminal, and a storage medium are provided, belonging to the technical field of computers. The method includes: extracting time-sequence feature information between first target frame images in a video, the time-sequence feature information being information determined based on the feature differences of the first target frame images at different time points; generating, based on to the time-sequence feature information, a dynamic event description text for describing a dynamic event corresponding to the video; and determining, based on the dynamic-event description text, a video tag of the video.

Abstract: Provided is a low-molecular-weight holothurian glycosarninoglycan, with the constituent units thereof being a glucuronic acid group, an N-acetaminogalactose group and a fucose group, and a sulfate ester group or acetyl ester group thereof. Glucuronic acid and N-acetaminogalactose are interconnected via ?(1-3) and ?(1-4) glucosidic bonds to form a backbone of a disaccharide repeating structural unit, and a fucose group is connected to the backbone as a side chain. On a molar ratio basis, the ratio of the glucuronic acid group:the N-acetaminogalactose group:the fucose group is 1:(0.8-1.2):(0.6-1.2). In the structure of the low-molecular-weight holothurian glycosaminoglycan, 10-30% of glucuronic acid groups are modified, on the 2-position, with a sulfate ester group, and the rest are hydroxyl groups; and a proportion of 10-30% of fucose groups is modified, on the 2-position, with an acetyl ester group, and the rest are hydroxyl or sulfate ester groups.

Abstract: A stabilization degree adjustment method includes obtaining a stabilization degree adjustment instruction and adjusting a stabilization degree of a stabilization mechanism according to the stabilization degree adjustment instruction. The stabilization mechanism is configured to support a load.

Abstract: An electronic device may include first and second phased antenna arrays that convey radio-frequency signals at frequencies greater than 10 GHz. The second array may have fewer antennas than the first array. Control circuitry may control the first and second arrays in a diversity mode and in a simultaneous array mode. In the diversity mode, the first array may form a first signal beam while the second array is inactive. When the first array is blocked by an object or otherwise exhibits unsatisfactory performance, the second array may form a second signal beam while the first array is inactive. In the simultaneous mode, the first and second arrays may form a combined array that produces a third signal beam. The combined array may maximize gain. Hierarchical beam searching operations may be performed. The arrays may be distributed across one or more modules.

Abstract: A method of manufacturing a semiconductor structure includes: forming a light-absorption layer in a substrate; forming a first doped region of a first conductivity type and a second doped region of a second conductivity type in the light-absorption layer adjacent to the first doped region; depositing a first patterned mask layer over the light-absorption layer, wherein the first patterned mask layer includes an opening exposing the second doped region and covers the first doped region; forming a first silicide layer in the opening on the second doped region; depositing a barrier layer over the first doped region; and annealing the barrier layer to form a second silicide layer on the first doped region.

Abstract: The invention belongs to the field of low-power consumption Bluetooth technology in wireless communication, in particular to a method for improving the sensitivity of the receiver in a low-power consumption Bluetooth system. The method of the invention is to introduce a deinterleaver between the symbol pattern mapper and GFSK modulator of the transmitting terminal under the low-power consumption Bluetooth coding mode, which is used to perform additional processing on the bitstream data and then perform modulation; then, due to the introduction of interleaving, Turbo iterative processing of demodulation and decoding can be performed at the receiving terminal; the receiving terminal comprises a Turbo iterative demodulator and decoder, which is used to model the low-power consumption Bluetooth GFSK modulator and convolutional coder into finite state machines, and then combine the deinterleaver to use the BCJR algorithm for iterative demodulation and decoding.