Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a buffer layer between the channel layer and the substrate. The method can further include forming a recess structure in the channel layer. The recess structure can include a bottom surface over the buffer layer. The method can further include forming a first epitaxial layer over the bottom surface of the recess structure. The first epitaxial layer can include a first atomic concentration of germanium. The method can further include forming a second epitaxial layer over the first epitaxial layer. The second epitaxial layer can include a second atomic concentration of germanium greater than the first atomic concentration of germanium.

Abstract: Intelligent process management is provided. A start time is determined for an additional process to be run on a worker node within a duration of a sleep state of a task of a process already running on the worker node by adding a first defined buffer time to a determined start time of the sleep state of the task. A backfill time is determined for the additional process by subtracting a second defined buffer time from a determined end time of the sleep state of the task. A scheduling plan is generated for the additional process based on the start time and the backfill time corresponding to the additional process. The scheduling plan is executed to run the additional process on the worker node according to the start time and the backfill time corresponding to the additional process.

Abstract: Aspects of the subject technology relate to systems, methods, and computer-readable media for identifying a borehole correction factor for determining a true resistivity by selecting a model to apply in identifying the borehole correction factor and applying the model to an apparent resistivity to identify the borehole correction factor. To perform borehole correction, a multiplicative coefficient is needed to apply to the apparent resistivity. A database of this multiplicative coefficient, called the borehole correction factor, is generated based on the borehole correction model. The technology described herein allows operators to avoid time-consuming variable borehole diameter sweeps and complex borehole diameter inversion current used in resistivity logging software.

Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.

Abstract: Systems and methods of the present disclosure relate to calibration of resistivity logging tool. A method to calibrate a resistivity logging tool comprises disposing the resistivity logging tool into a formation; acquiring a signal at each logging point with the resistivity logging tool; assuming a formation model for a first set of continuous logging points in the formation; inverting all of the signals for unknown model parameters of the formation model, wherein the formation model is the same for all of the continuous logging points in the first set; assigning at least one calibration coefficient to each type of signal, wherein the calibration coefficients are the same for the first set; and building an unknown vector that includes the unknown model parameters and the calibration coefficients, to calibrate the resistivity logging tool.

Abstract: The disclosure relates to a method performed by an electronic device of a base station. The method includes: obtaining beam priority information of a plurality of beams for a plurality of user equipments (UEs); obtaining inter-beam interference information of the plurality of beams; identifying, based on the beam priority information and the inter-beam interference information, one of a plurality of beam pairing sets comprising two or more beams among the plurality of beams; and performing communication with at least one of the plurality of UEs via the identified beam pairing set.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a buffer layer between the channel layer and the substrate. The method can further include forming a recess structure in the channel layer. The recess structure can include a bottom surface over the buffer layer. The method can further include forming a first epitaxial layer over the bottom surface of the recess structure. The first epitaxial layer can include a first atomic concentration of germanium. The method can further include forming a second epitaxial layer over the first epitaxial layer. The second epitaxial layer can include a second atomic concentration of germanium greater than the first atomic concentration of germanium.

Abstract: Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.

Abstract: A device includes first and second semiconductor fins, first, second, third and fourth fin sidewall spacers, and first and second epitaxy structures. The first and second fin sidewall spacers are respectively on opposite sides of the first semiconductor fin. The third and fourth fin sidewall spacers are respectively on opposite sides of the second semiconductor fin. The first and third fin sidewall spacers are between the first and second semiconductor fins and have smaller heights than the second and fourth fin sidewall spacers. The first and second epitaxy structures are respectively on the first and second semiconductor fins and merged together.

Abstract: A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.

Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a semiconductor substrate, a first fin and a second fin extending from the semiconductor substrate, a first lower semiconductor feature over the first fin, a second lower semiconductor feature over the second fin. Each of the first and second lower semiconductor features includes a top surface bending downward towards the semiconductor substrate in a cross-sectional plane perpendicular to a lengthwise direction of the first and second fins. The semiconductor device also includes an upper semiconductor feature over and in physical contact with the first and second lower semiconductor features, and a dielectric layer on sidewalls of the first and second lower semiconductor features.

Abstract: A method and system for identifying a blind spot in one or more decoupled measurements. The method may comprise disposing an electromagnetic well measurement system into a wellbore. The electromagnetic well measurement system comprise an electromagnetic transmitter and a plurality of electromagnetic receivers. The method may further comprise transmitting electromagnetic fields into a formation with the electromagnetic transmitter, measuring the electromagnetic fields with the plurality of electromagnetic receivers as one or more measurements at one or more depths in the wellbore, decoupling the one or more measurements to form decoupled measurements, identifying if a blind spot is in the decoupled measurements, and performing an inversion with the decoupled measurements.

Abstract: The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics. The method includes forming a fin structure that includes an epitaxial layer portion and a doped region portion surrounded by an isolation region so that a top section of the epitaxial layer portion is above the isolation region. The method also includes depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region and annealing the silicon-based layer to reflow the silicon-based layer. The method further includes etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region and annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region.

Abstract: A lighting structure includes a surface cover plate, a lighting module, a light adjustment layer, an optical adhesive layer and an electronic paper display module. The surface cover plate has a visible area and a black bezel. The lighting module has a light guide plate and point light sources. The light adjustment layer has an optical thinning region and a frame-shaped adhesive. The optical thinning region is less than the light guide plate in refractive index. The surface cover plate and the lighting module are adhered by the frame-shaped adhesive. The optical thinning region is disposed on an upper surface of the light guide plate. The optical adhesive layer has a refractive index equal to or greater than a refractive index of the light guide plate. The electronic paper display module is disposed under the lighting module.

Abstract: Apparatus and methods for measuring the oil to water ratio of a wellbore fluid. An example method includes flowing the wellbore fluid into a flow path of a fluid identification device disposed on the outside of a wellbore tubing and within a wellbore annulus. The fluid identification device comprises a shroud, the flow path disposed within the shroud that opens to the wellbore annulus and fluidically links the wellbore annulus to the wellbore tubing thereby allowing fluid flow through the flow path from the wellbore annulus to the wellbore tubing, and an alternating current electrical sensor disposed within the flow path. The method further includes measuring a property of the wellbore fluid with the alternating current electrical sensor when the wellbore fluid has flowed into the flow path and determining the oil to water ratio of the wellbore fluid that flowed through the flow path.

Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

Abstract: A semiconductor device includes a substrate, a semiconductor feature protruding from the substrate and extending lengthwise in a first direction, an epitaxial feature directly above the semiconductor feature, and a gate stack adjacent the epitaxial feature. The epitaxial feature comprises a lower portion and an upper portion over the lower portion. The upper portion extends partially through the lower portion in a cross section perpendicular to the first direction. A topmost surface of the upper portion is substantially flat.

Abstract: A hyperspectral characteristic band selection method and an active hyperspectral imaging device using the same. The method using a virtual dimension algorithm to calculate a number of endmembers of a hyperspectral image of a predetermined disease, and using between 1 time and 2 times the number of endmembers as a number of predetermined selected bands, and then selecting characteristic bands with a number matching the number of selected bands from a plurality of spectral bands in the image. The device comprises a base, light sources and a sensing portion, the light sources are respectively disposed on the base, bands emitted by the light sources are configured according to the characteristic bands calculated by the method. The sensing portion is disposed on the base and spaced apart from the light sources for receiving reflected light from an external target object irradiated by the light sources to obtain a hyperspectral image.

Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

Abstract: The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics. The method includes forming a fin structure that includes an epitaxial layer portion and a doped region portion surrounded by an isolation region so that a top section of the epitaxial layer portion is above the isolation region. The method also includes depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region and annealing the silicon-based layer to reflow the silicon-based layer. The method further includes etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region and annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region.