Abstract: An electronic device and a power saving method of the electronic device are provided. The power saving method includes following steps. A wake-up event is received in a low power consumption mode. Whether the wake-up event is an unexpected wake-up event is determined. Battery statistic data are analyzed to generate an analysis result when the wake-up event is the unexpected wake-up event. A status of a plurality of background applications operating in a background is adjusted according to the analysis result.

Abstract: A semiconductor device has a first substrate with a surface. A thickness of the first substrate is less than 120 micrometers. The surface undergoes a grinding operation. The surface of the first substrate is then polished to produce a polished surface. The first substrate is singulated into a plurality of semiconductor die. The semiconductor die is over an interposer. The interposer has a second substrate and a conductive via formed through the second substrate. The interposer further has a first insulating layer formed over a first surface of the second substrate, first conductive layer formed over the first surface, second insulating layer formed over a second surface of the second substrate, second conductive layer formed over the second surface, and bump formed over the second conductive layer. An underfill material is deposited around the semiconductor die. The polished surface inhibits progression of the underfill material onto the polished surface.

Abstract: A semiconductor manufacturing equipment has a wafer tape including a plurality of alignment holes formed through the wafer tape. A semiconductor wafer is disposed over the wafer tape. The semiconductor wafer includes a circular or rectangular form-factor. A light source is disposed under the wafer tape. The semiconductor wafer is misaligned on the wafer tape with light passing through one or more alignment holes. The semiconductor wafer is centered on the wafer tape with no light passing through one or more alignment holes. The wafer tape has a plurality of wafer alignment markings for different size semiconductor wafers. A light detector is disposed over the semiconductor wafer to detect light passing through the wafer tape. A control arm can be attached to the semiconductor wafer to provide the ability to move the semiconductor wafer in response to a control signal from the light detector.

Abstract: Present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor fin and a metal gate. The semiconductor fin has a first portion and a second portion over the first portion. A height of the second portion is greater than a width of the second portion. The metal gate has a bottom portion, an upper portion, and a lateral portion connecting the bottom portion and the upper portion. The bottom portion is between the first portion and the second portion of the semiconductor fin, and the upper portion is over the second portion of the semiconductor fin.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first barrier layer is formed on the gate dielectric layer, a second barrier layer is formed on the first barrier layer, a first work function adjustment layer is formed on the second barrier layer, the first work function adjustment layer and the second barrier layer are removed. After the first work function adjustment layer and the second barrier layer are removed, a second work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the second work function adjustment layer.

Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.

Abstract: Systems and methods for smoothing a resistivity log are disclosed. An azimuthal resistivity tool measures azimuthal impedances at multiple azimuthal angles around a wellbore axis at each depth. It is determined whether the drill string was in a drilling mode or a sliding mode at the depth. If the drill string was in the drilling mode, a co-axial component and a lateral component are determined based in part on the azimuthal impedances associated with the depth and the lateral component is stored. If the drill string was in the sliding mode, a second co-axial component is determined based in part on at least one of the plurality of azimuthal impedances and a previously stored lateral component. The resistivity log is plotted from resistivities determined from the first and second co-axial components at each depth.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, an active region on the substrate, and a gate structure, a source conductor, and a drain conductor disposed on the active region. The semiconductor device further comprises a first type doped region of the active region below the gate structure and a second type doped region of the active region adjacent to the first type doped region, and the first type doped region is different from the second type doped region. The second type doped region is configured to function as a resistor.

Abstract: Present disclosure provides a method including: forming a semiconductor stack having at least one SiGe layer; forming a plurality of fins from the semiconductor stack by a first etching operation, each of the plurality of fins comprising a first portion and a second portion over the first portion, the first portion being separated from the second portion by a SiGe portion; forming a poly gate stripe orthogonally over the plurality of fins; forming a recess on each of the plurality of fins abutting the poly gate; recessing the SiGe portion by a second etching operation through the recess; forming a first spacer and a second spacer to surround the SiGe portion; and removing the SiGe portion.

Abstract: A semiconductor device has an electrical component and an e-bar structure disposed to a side of the electrical component. An encapsulant is deposited over the electrical component and e-bar structure. An RDL is formed over the electrical component, encapsulant, and e-bar structure. The e-bar structure has a core layer, a first conductive layer formed over a first surface of the core layer, and a second conductive layer formed over a second surface of the core layer. The second conductive layer includes a thickness greater than the first conductive layer. The RDL has an insulating layer formed over the electrical component and encapsulant, and a conductive layer formed over the insulating layer. A bump is formed over a contact pad of the e-bar structure opposite the RDL. A contact pad of the electrical component is electrically connected to the RDL opposite the bump.

Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first barrier layer is formed on the gate dielectric layer, a second barrier layer is formed on the first barrier layer, a first work function adjustment layer is formed on the second barrier layer, the first work function adjustment layer and the second barrier layer are removed. After the first work function adjustment layer and the second barrier layer are removed, a second work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the second work function adjustment layer.

Abstract: An apparatus for non-contact measuring temperature includes a stand, for securing a vapor chamber, wherein the vapor chamber comprises a condenser area and an evaporator area, wherein the evaporator area comprises a heating spot; a continuous-wave laser device, facing the stand, for irradiating the heating spot by providing an infrared laser beam, wherein the infrared laser beam comprises a first infrared wavelength range; a switch device, controlling an irradiating cycle of the infrared laser beam, wherein the irradiating cycle comprises a irradiating time-interval and a non-irradiating time-interval; a first infrared sensor, facing the stand, for collecting a first thermal radiation data of the heating spot in a second infrared wavelength range; a data processing unit, only transferring the first thermal radiation data in the non-irradiating time-interval into a first temperature, wherein the irradiating time-interval is longer than the non-irradiating time-interval.

Abstract: A device includes a semiconductor channel region over a substrate, a shallow trench isolation (STI) region in the substrate, a gate structure over the semiconductor channel region. The semiconductor channel region has a channel top higher than a top surface of the STI region by a first height. The device further includes a first source/drain epitaxy structure and a second source/drain epitaxy structure respectively at opposite sides of the gate structure, and a first dielectric fin sidewall structure and a second dielectric fin sidewall structure on opposite sides of the first source/drain epitaxy structure, respectively. A top of the first dielectric fin sidewall structure is higher than the top surface of the STI region by a second height. The second height is at most half the first height.

Abstract: An object recognition unit (200) recognizes an object existing around a moving body (100). A surrounding situation estimation unit (204) analyzes at least any of a position and behavior of the object recognized by the object recognition unit (200), and derives as a latent event, an event which is likely to surface later and is attributed to an object that the object recognition unit (200) has not been able to recognize to exist around the moving body (100).

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate, an active region on the substrate, and a first transistor having a gate structure, a source conductor, and a drain conductor disposed on the active region, wherein the drain conductor and the source conductor are disposed on opposite sides of the gate structure, and the source conductor is shorter than the drain conductor.

Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.

Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

Abstract: Systems and methods for separating and orienting foodstuff using a tank of liquid, mechanical parts, machine vision, and artificial intelligence (AI) modeling. The system employs a tank comprising liquid, strategically placed liquid jets, and a lifting device with a grid plate. Foodstuff batches enter the tank. The submerged grid plate receives the foodstuff, and the liquid jets manipulate them inside the tank. Buoyancy and strategically directed liquid flow separate and orient the individual food items. A mechanical arm equipped with a gripper and other mechanical apparatus manipulates and transports the foodstuff outside the tank. AI models trained on image data depicting the singulation process are used. The AI model guides the system to achieve optimal separation and orientation of the foodstuff, resulting in individually separated and oriented foodstuff units.

Abstract: A liquid pump includes a pump house with an electric motor housed therein, a pump cover connected to the pump house, an impeller housed in the pump cover and driven by the motor, and a sleeve disposed between the pump cover and the pump house. Two of the pump cover, the pump house, and the sleeve are respectively provided with an outer binding segment and an inner binding segment, the outer binding segment is made of polyphenylene sulfide mixed with glass fiber, and permeable to a laser light, the inner binding segment is capable of absorbing the laser light.

Abstract: The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.