Abstract: A system and a method for evaluating a subterranean earth formation include a logging tool locatable in a wellbore dispose in the formation. The logging tool may include a transmitter antenna and a single receiver antenna. The transmitter antenna is configured to transmit a first electromagnetic signal into the subterranean earth formation. The system further includes a processor and a non-transitory memory device. The memory device includes instructions that cause the processor to control a current and a voltage sourced to the transmitter antenna, receive, via the single receiver antenna, a second electromagnetic signal emitted by the subterranean earth formation in response to receiving the first electromagnetic signal, and determine a resistivity of the subterranean earth formation based on the second electromagnetic signal.

Abstract: The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

Abstract: A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.

Abstract: A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, an insulating stack formed over the substrate, a vertical structure formed through the insulating stack, a source/drain region formed over the vertical structure, and an isolation structure formed adjacent to the source/drain region and protruding the insulating stack. The source/drain region can include a first side surface and a second side surface. A lateral separation between the first side surface and the vertical structure can be greater than an other lateral separation between the second side surface and the vertical structure.

Abstract: A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.

Abstract: a stator core, a bobbin fixed on the stator core, and a plurality of windings wound on the bobbin, characterized in that the stator further comprises an elastic member with one end fixed onto the insulating frame, the other end of the elastic member is resisted against and thereby forcing the bobbin to axially position the stator.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. A sacrificial gate layer is removed to form a gate trench exposing a sacrificial dielectric layer. An ion implantation is performed to a portion of a substrate covered by the sacrificial dielectric layer in the gate trench. The sacrificial dielectric layer is removed to expose the substrate from the gate trench. An interfacial layer is formed over the substrate in the gate trench. A metal gate structure is formed over the interfacial layer in the gate trench.

Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a substrate, an isolation structure over the substrate, a fin extending from the substrate, and an epitaxial feature over the fin. The epitaxial feature comprises a lower portion and an upper portion. The lower portion extends from the fin and extends above the isolation structure. The upper portion is over the lower portion. The upper portion extends partially through the lower portion in a cross section perpendicular to a lengthwise direction of the fin.

Abstract: A system described herein may provide a technique for handling call requests, prior to the performance of a call setup procedure, based on attributes of a calling User Equipment (“UE”) and/or a called UE. A Messaging Application Server may receive a call request, from the calling UE and to the called UE, identify a category or event type associated with the call request, and notify the called UE of the call request, including the category or event type. Different categories or event types may be associated with different sets of eligible actions to perform. The called UE may indicate a particular action, associated with the identified category or event type, and the MAS may handle the call request according to the particular action (e.g., reject the call request or proceed with a call setup procedure).

Abstract: A liquid pump includes a pump house with an electric motor housed therein, a pump cover connected to the pump house, an impeller housed in the pump cover and driven by the motor, and a sleeve disposed between the pump cover and the pump house. Two of the pump cover, the pump house, and the sleeve are respectively provided with an outer binding segment and an inner binding segment, the outer binding segment is made of polyphenylene sulfide mixed with glass fiber, and permeable to a laser light, the inner binding segment is cable of absorbing the laser light.

Abstract: A device includes first and second semiconductor fins, first, second, third and fourth fin sidewall spacers, and first and second epitaxy structures. The first and second fin sidewall spacers are respectively on opposite sides of the first semiconductor fin. The third and fourth fin sidewall spacers are respectively on opposite sides of the second semiconductor fin. The first and third fin sidewall spacers are between the first and second semiconductor fins and have smaller heights than the second and fourth fin sidewall spacers. The first and second epitaxy structures are respectively on the first and second semiconductor fins and merged together.

Abstract: A static random access memory (SRAM) cell includes a semiconductor fin, a first gate structure, a second gate structure, an epitaxy structure, and a first fin sidewall structure. The first gate structure crosses the semiconductor fin to form a pull-down (PD) transistor. The second gate structure crosses the semiconductor fin to form a pull-gate (PG) transistor. The epitaxy structure is on the semiconductor fin and between the first and second gate structures. The first fin sidewall structure is on a first side of the epitaxy structure and between the first and second gate structures. A method for manufacturing the semiconductor device is also disclosed.

Abstract: A method of preparation and application for a glass ceramic sealing thin strip with high sealing performance, differing from using conventional glass ceramic packaging paste applied to the junction of the cell stack assembly and connecting plates. The glass ceramic sealing thin strip of present invention utilizes tape casting to produce a single layer or multi-layer stacking in accordance with the required thickness of the glass-ceramic sealing thin strip, and cutting the glass ceramic sealing thin strips from molds in accordance with the geometry of cell stacks with equal thickness of the glass ceramic sealing thin strip for SOFC cell stack assembly, aiming to overcome the setbacks of the conventional dispensing method with glass ceramic packaging paste that makes the thickness difficult to control, and to effectively improve sealing performance of the cell stack assembly and the power generation efficiency, and achieve commercial application with mass production.

Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first epitaxial source/drain region in the first fin and adjacent the first gate spacer. The first epitaxial source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer including silicon and carbon, a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin, and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer.

Abstract: The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics. The method includes forming a fin structure that includes an epitaxial layer portion and a doped region portion surrounded by an isolation region so that a top section of the epitaxial layer portion is above the isolation region. The method also includes depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region and annealing the silicon-based layer to reflow the silicon-based layer. The method further includes etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region and annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region.

Abstract: A method for manufacturing an integrated circuit is provided. The method includes forming first and second semiconductor fins; forming first and second dielectric fin sidewall structures on opposite sidewalls of the first semiconductor fin, wherein the first dielectric fin sidewall structure is higher than the second dielectric fin sidewall structure, and the second dielectric fin sidewall structure is between the first and second semiconductor fins; recessing at least a portion of the first semiconductor fin between the first and second dielectric fin sidewall structures until a top of the recessed portion of the first semiconductor fin is lower than a top of the first dielectric fin sidewall structure; and forming a first epitaxy structure on the recessed portion of the first semiconductor fin.

Abstract: A semiconductor device and method of forming the same are disclosed. The method of forming a semiconductor device includes providing a substrate, an isolation structure over the substrate, and at least two fins extending from the substrate and through the isolation structure; etching the at least two fins, thereby forming at least two trenches; growing first epitaxial features in the at least two trenches; growing second epitaxial features over the first epitaxial features in a first growth condition; and after the second epitaxial features reach a target critical dimension, growing the second epitaxial features in a second growth condition different from the first growth condition.

Abstract: The disclosure relates to an electric liquid pump, comprising a pump housing, a motor connected to the pump housing, and an impeller housed in the pump housing and driven by the motor. The pump housing is provided with an inlet port and an outlet port. The impeller has an impeller inlet at the center thereof and an impeller outlet at a peripheral side thereof. The inlet port, the impeller inlet, the impeller outlet, and the outlet port are in flow connection sequentially. The inlet port comprises a columnar first segment and a second segment extending from the first segment. The second segment is close to the impeller inlet with a mouting seat formed therein. The impeller is sleeved on a rotation shaft. One end of the rotation shaft is engaged in the mounting seat. The impeller is rotatable relative to the mounting seat. The mounting seat is partially received in the impeller inlet. A gap between the mounting seat and an inner wall of the impeller inlet is defined as a flow passage for liquid.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, an insulating stack formed over the substrate, a vertical structure formed through the insulating stack, a source/drain region formed over the vertical structure, and an isolation structure formed adjacent to the source/drain region and protruding the insulating stack. The source/drain region can include a first side surface and a second side surface. A lateral separation between the first side surface and the vertical structure can be greater than an other lateral separation between the second side surface and the vertical structure.