Patents by Inventor Yi Jing

Yi Jing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11249789
    Abstract: A computer-implemented hypervisor system and method comprises utilizing the hypervisor system, which comprises a privileged domain (PD) and a guest domain (GD). The PD is an instance of a virtual machine that has direct access to hardware devices. The PD comprises a back-end interface for communicating with other GDs. The GD is an instance of a virtual machine that does not have direct access to hardware devices, and comprises a front-end interface for communicating with the PD and communicates only packets with the PD. On the GD, and in an initialization stage of the front-end interface, the system allocates a predefined number of packet data entries for storing packet data, allocates the predefined number of grant table entries, each comprising a grant table id. During the initialization stage, each grant table entry is bound with a packet data entry.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: February 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: Mo Zhou, He Jing, XingYu Zhu, Yi Jing Zhu
  • Publication number: 20220045198
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include a channel layer and a buffer layer between the channel layer and the substrate. The method can further include forming a recess structure in the channel layer. The recess structure can include a bottom surface over the buffer layer. The method can further include forming a first epitaxial layer over the bottom surface of the recess structure. The first epitaxial layer can include a first atomic concentration of germanium. The method can further include forming a second epitaxial layer over the first epitaxial layer. The second epitaxial layer can include a second atomic concentration of germanium greater than the first atomic concentration of germanium.
    Type: Application
    Filed: April 1, 2021
    Publication date: February 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Heng LI, Yi-Jing Li, Chia-Der Chang
  • Publication number: 20220045190
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first barrier layer is formed on the gate dielectric layer, a second barrier layer is formed on the first barrier layer, a first work function adjustment layer is formed on the second barrier layer, the first work function adjustment layer and the second barrier layer are removed. After the first work function adjustment layer and the second barrier layer are removed, a second work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the second work function adjustment layer.
    Type: Application
    Filed: October 25, 2021
    Publication date: February 10, 2022
    Inventors: Yi-Jing LEE, Chih-Hsin KO, Clement Hsingjen WANN
  • Publication number: 20220037682
    Abstract: A method of preparation and application for a glass ceramic sealing thin strip with high sealing performance, differing from using conventional glass ceramic packaging paste applied to the junction of the cell stack assembly and connecting plates. The glass ceramic sealing thin strip of present invention utilizes tape casting to produce a single layer or multi-layer stacking in accordance with the required thickness of the glass-ceramic sealing thin strip, and cutting the glass ceramic sealing thin strips from molds in accordance with the geometry of cell stacks with equal thickness of the glass ceramic sealing thin strip for SOFC cell stack assembly, aiming to overcome the setbacks of the conventional dispensing method with glass ceramic packaging paste that makes the thickness difficult to control, and to effectively improve sealing performance of the cell stack assembly and the power generation efficiency, and achieve commercial application with mass production.
    Type: Application
    Filed: August 3, 2020
    Publication date: February 3, 2022
    Inventors: TAI-NAN LIN, SZU-HAN WU, YI-JING WU, MIN-FANG HAN, WEI-XIN KAO, HONG-YI KUO, CHUN-YEN YEH, YUNG-NENG CHENG, RUEY-YI LEE
  • Publication number: 20220006360
    Abstract: A fluid pump includes a pump casing, a motor connected to the pump casing, and an impeller driven by the motor. The motor includes a housing and a stator arranged in the casing. The housing is made of a non-magnetic material. The stator includes a stator iron core and a plurality of windings wound on the stator iron core. The motor further includes a sleeve having a cylindrical main body and a flange extending radially outwards from one end of the main body and fixed to the housing. An annular space is jointly bounded by the sleeve and the housing to accommodate the stator. A part of inner surface of the housing and a part of bottom surface of the flange facing the annular space are coated with a metal coating for electromagnetic wave shielding.
    Type: Application
    Filed: September 17, 2021
    Publication date: January 6, 2022
    Inventors: Xiaoming WANG, Long YU, Pinghua TANG, Yi JING, Ruifeng QIN, Guoyuan ZOU
  • Publication number: 20210375693
    Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.
    Type: Application
    Filed: April 8, 2021
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: I-Sheng CHEN, Yi-Jing LI, Chen-Heng LI
  • Patent number: 11189697
    Abstract: The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics. The method includes forming a fin structure that includes an epitaxial layer portion and a doped region portion surrounded by an isolation region so that a top section of the epitaxial layer portion is above the isolation region. The method also includes depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region and annealing the silicon-based layer to reflow the silicon-based layer. The method further includes etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region and annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sherry Li, Chia-Der Chang, Yi-Jing Lee
  • Publication number: 20210356283
    Abstract: A traveling situation extraction unit (120) extracts, from a traffic accident database in which traffic accident scene information expressing a situation of a traffic accident scene is accumulated, a traveling situation of a vehicle corresponding to a traffic accident scene. An avoidance route generation unit (130) generates a plurality of avoidance routes to avoid the traffic accident scene on the basis of the traveling situation. An effectiveness determination unit (140) determines, for each of the plurality of avoidance routes, a value that expresses effectiveness, as an effective evaluation value. An effective route selection unit (150) selects a most effective avoidance route as an effective route from among the plurality of avoidance routes on the basis of an effective evaluation value of each of the plurality of avoidance routes.
    Type: Application
    Filed: July 27, 2021
    Publication date: November 18, 2021
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shu MURAYAMA, Yi JING
  • Publication number: 20210344730
    Abstract: A system described herein may provide a technique for handling call requests, prior to the performance of a call setup procedure, based on attributes of a calling User Equipment (“UE”) and/or a called UE. A Messaging Application Server may receive a call request, from the calling UE and to the called UE, identify a category or event type associated with the call request, and notify the called UE of the call request, including the category or event type. Different categories or event types may be associated with different sets of eligible actions to perform. The called UE may indicate a particular action, associated with the identified category or event type, and the MAS may handle the call request according to the particular action (e.g., reject the call request or proceed with a call setup procedure).
    Type: Application
    Filed: May 4, 2020
    Publication date: November 4, 2021
    Inventors: Yi Jing, Timothy M. Dwight, Lulia Ann Barakat
  • Patent number: 11164538
    Abstract: The disclosure provides a storage medium, an expansion base and an operation method thereof combined with a portable electronic device. The portable electronic device is pre-installed with an application program and includes a touch screen. The expansion base is paired with the portable electronic device and accommodates the portable electronic device. When the portable electronic device is accommodated inside the expansion base, a touch window on the surface of the expansion base exposes at least a portion of the touch screen, and the portable electronic device executes the application program to automatically adjust a size or a display position of a display image of the touch screen to correspond to the touch window.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: November 2, 2021
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Che-Wei Liang, Xiu-Yu Lin, Yi-Han Liao, Sheng-Chieh Tang, Chieh-Yu Chan, Chiao-Tsu Chiang, Wen-Yi Chiu, Wei-Chih Hsu, Li-Fang Chen, Yi-Jing Lin
  • Patent number: 11158719
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first barrier layer is formed on the gate dielectric layer, a second barrier layer is formed on the first barrier layer, a first work function adjustment layer is formed on the second barrier layer, the first work function adjustment layer and the second barrier layer are removed. After the first work function adjustment layer and the second barrier layer are removed, a second work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the second work function adjustment layer.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: October 26, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Chih-Shin Ko, Clement Hsingjen Wann
  • Publication number: 20210328047
    Abstract: In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Inventors: Yi-Jing Lee, Ming-Hua Yu
  • Publication number: 20210313230
    Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a semiconductor substrate, a first fin and a second fin extending from the semiconductor substrate, a first lower semiconductor feature over the first fin, a second lower semiconductor feature over the second fin. Each of the first and second lower semiconductor features includes a top surface bending downward towards the semiconductor substrate in a cross-sectional plane perpendicular to a lengthwise direction of the first and second fins. The semiconductor device also includes an upper semiconductor feature over and in physical contact with the first and second lower semiconductor features, and a dielectric layer on sidewalls of the first and second lower semiconductor features.
    Type: Application
    Filed: June 14, 2021
    Publication date: October 7, 2021
    Inventors: Yi-Jing Lee, Jeng-Wei Yu, Li-Wei Chou, Tsz-Mei Kwok, Ming-Hua Yu
  • Publication number: 20210313428
    Abstract: The present disclosure describes a method for forming ultra-thin fins with a tapered bottom profile for improved structural rigidity and gate control characteristics. The method includes forming a fin structure that includes an epitaxial layer portion and a doped region portion surrounded by an isolation region so that a top section of the epitaxial layer portion is above the isolation region. The method also includes depositing a silicon-based layer on the top portion of the epitaxial layer above the isolation region and annealing the silicon-based layer to reflow the silicon-based layer. The method further includes etching the silicon-based layer and the fin structure above the isolation region to form a first bottom tapered profile in the fin structure above the isolation region and annealing the fin structure to form a second bottom tapered profile below the first bottom tapered profile and above the isolation region.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sherry LI, Chia-Der Chang, Yi-Jing Lee
  • Patent number: 11097158
    Abstract: A gait training machine includes a base, a driving module including a driving circuit, a motor and two moving platforms, a sensor module including a left pedal, a right pedal, a plurality of pressure sensors and a position sensor, a controller electrically connected to the driving circuit, each pressure sensor and the position sensor and a signal processing module disposed in the controller and including a gait detecting unit and a gait determining unit with a center-of-gravity calculation logic and a gait determining logic stored therein. Using the above gait training machine to determine whether the bearing weight of the left pedal and the right pedal is correct, and whether the center-of-gravity position is correct, so that the user can know the ankle joint movement and the center-of-gravity during gait training to adjust the health gait posture.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 24, 2021
    Assignee: HIWIN TECHNOLOGIES CORP.
    Inventors: Chao-Ju Huang, Jia-Ming Shiu, Yi-Jing Wu
  • Publication number: 20210233906
    Abstract: A semiconductor device with an isolation structure and a method of fabricating the same are disclosed. The semiconductor device includes first and second fin structures disposed on a substrate and first and second pairs of gate structures disposed on the first and second fin structures. The first end surfaces of the first pair of gate structures face second end surfaces of the second pair of gate structure. The first and second end surfaces of the first and second pair of gate structures are in physical contact with first and second sidewalls of the isolation structure, respectively. The semiconductor device further includes an isolation structure interposed between the first and second pairs of gate structures. An aspect ratio of the isolation structure is smaller than a combined aspect ratio of the first pair of gate structures.
    Type: Application
    Filed: July 23, 2020
    Publication date: July 29, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Shuo CHEN, Chia-Der CHANG, Yi-Jing LEE
  • Publication number: 20210216523
    Abstract: This application discloses a data storage method, a metadata server, and a client. The method includes: A first client sends a first lock request for locking a first data range of a first file to a metadata server. The metadata server receives the first lock request sent by the first client. If the first data range of the first file is not locked, the metadata server locks the first data range of the first file, and sends a first lock response to the first client, to indicate that the first data range of the first file is locked by the first client. According to this application, a client may actively request the metadata server to lock a data range of a file, so that a range of a file can be more flexibly locked.
    Type: Application
    Filed: March 29, 2021
    Publication date: July 15, 2021
    Inventor: Yi Jing
  • Publication number: 20210206917
    Abstract: The present invention relates to a carboxyl group containing perfluoropolyether compound of formula (I): Rf—X1—X2(I). In the formula Rf—X1—X2(I), Rf represents F—(CF2)m—(OC4F8)p—(OC3F6)q—(OC2F4)r—(OCF2)s—OC(Z)F—(CF2)n—, wherein p, q, r and s are each independently an integer of 0 or more and 200 or less, and the sum of p, q, r and s is at least 1; in the formula, the occurrence order and number of the respective repeating units in parentheses with the subscript p, q, r or s are arbitrary in the formula; m and n are each independently an integer of 0 or more and 30 or less, Z is F or CF3; X1 represents a divalent organic group; and X2 represents a COOH group.
    Type: Application
    Filed: May 7, 2019
    Publication date: July 8, 2021
    Applicant: Guangzhou ur Materials Technology Co., Ltd.
    Inventors: Yi-Jing CHEN, Qi-Guan WANG, Gong-Zhou CHEN
  • Publication number: 20210208917
    Abstract: A computer-implemented hypervisor system and method comprises utilizing the hypervisor system, which comprises a privileged domain (PD) and a guest domain (GD). The PD is an instance of a virtual machine that has direct access to hardware devices. The PD comprises a back-end interface for communicating with other GDs. The GD is an instance of a virtual machine that does not have direct access to hardware devices, and comprises a front-end interface for communicating with the PD and communicates only packets with the PD. On the GD, and in an initialization stage of the front-end interface, the system allocates a predefined number of packet data entries for storing packet data, allocates the predefined number of grant table entries, each comprising a grant table id. During the initialization stage, each grant table entry is bound with a packet data entry.
    Type: Application
    Filed: January 6, 2020
    Publication date: July 8, 2021
    Inventors: Mo Zhou, He Jing, XingYu Zhu, Yi Jing Zhu
  • Patent number: 11056578
    Abstract: In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jing Lee, Ming-Hua Yu