Abstract: Example data eviction methods and apparatus are described. One example method includes obtaining an access frequency and an access time of data, where the access frequency is a quantity of access times in a target time period, and the target time period is a part of an eviction period. An eviction priority of the data is determined based on the access frequency and the access time. The data is evicted in a cache system based on the eviction priority.

Abstract: A semiconductor device and method of forming the same are disclosed. The semiconductor device includes a substrate, an isolation structure over the substrate, a fin extending from the substrate, and an epitaxial feature over the fin. The epitaxial feature comprises a lower portion and an upper portion. The lower portion extends from the fin and extends above the isolation structure. The upper portion is over the lower portion. The upper portion extends partially through the lower portion in a cross section perpendicular to a lengthwise direction of the fin.

Abstract: The invention provides a self-modulating input electrical power laser control system and method. After the laser is turned on for a period of time, the control module reduces the initial electrical power to the operating power of the laser, and it maintains the operating power until the laser is turned off, which can reduce the extra power consumption and achieve the energy-efficiency.

Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.

Abstract: A fluid pump includes a pump casing, a motor connected to the pump casing, and an impeller driven by the motor. The motor includes a housing and a stator arranged in the casing. The housing is made of a non-magnetic material. The stator includes a stator iron core and a plurality of windings wound on the stator iron core. The motor further includes a sleeve having a cylindrical main body and a flange extending radially outwards from one end of the main body and fixed to the housing. An annular space is jointly bounded by the sleeve and the housing to accommodate the stator. A part of inner surface of the housing and a part of bottom surface of the flange facing the annular space are coated with a metal coating for electromagnetic wave shielding.

Abstract: In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.

Abstract: The present disclosure describes a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow-trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material to etch the first portion of the STI material at a first etching rate and the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material to etch the first portion of the STI material at a third etching rate and the second portion of the STI material at a fourth etching rate less than the third etching rate.

Abstract: A method for formation evaluation may comprise forming one or more model parameters from one or more priori geological information and one or more downhole measurements, identifying one or more inversion controls, and performing a forward model operation using a piecewise polynomial model (PPM). The method may further comprise performing an optimization using at least the forward model operation, the one or more model parameters, and the one or more inversion controls, determining if a misfit between the one or more downhole measurements and the one or more model parameters is greater than or less than a threshold, and updating the forward model operation or the one or more priori geological information based at least in part on the misfit.

Abstract: In a method for manufacturing a semiconductor device, an isolation insulating layer is formed over a fin structure. A first portion of the fin structure is exposed from and a second portion of the fin structure is embedded in the isolation insulating layer. A dielectric layer is formed over sidewalls of the first portion of the fin structure. The first portion of the fin structure and a part of the second portion of the fin structure in a source/drain region are removed, thereby forming a trench. A source/drain epitaxial structure is formed in the trench using one of a first process or a second process. The first process comprises an enhanced epitaxial growth process having an enhanced growth rate for a preferred crystallographic facet, and the second process comprises using a modified etch process to reduce a width of the source/drain epitaxial structure.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, an insulating stack formed over the substrate, a vertical structure formed through the insulating stack, a source/drain region formed over the vertical structure, and an isolation structure formed adjacent to the source/drain region and protruding the insulating stack. The source/drain region can include a first side surface and a second side surface. A lateral separation between the first side surface and the vertical structure can be greater than an other lateral separation between the second side surface and the vertical structure.

Abstract: A method and system for identifying a blind spot in one or more decoupled measurements. The method may comprise disposing an electromagnetic well measurement system into a wellbore. The electromagnetic well measurement system comprise an electromagnetic transmitter and a plurality of electromagnetic receivers. The method may further comprise transmitting electromagnetic fields into a formation with the electromagnetic transmitter, measuring the electromagnetic fields with the plurality of electromagnetic receivers as one or more measurements at one or more depths in the wellbore, decoupling the one or more measurements to form decoupled measurements, identifying if a blind spot is in the decoupled measurements, and performing an inversion with the decoupled measurements.

Abstract: A device includes a semiconductor substrate, a semiconductor fin, a gate structure, a first source/drain epitaxy structure, a second source/drain epitaxy structure, a first dielectric fin sidewall structure, a second dielectric fin sidewall structure. The semiconductor fin is over the semiconductor substrate. The semiconductor fin includes a channel portion and recessed portions on opposite sides of the channel portion. The gate structure is over the channel portion of the semiconductor fin. The first source/drain epitaxy structure and the second source/drain epitaxy structure are over the recessed portions of the semiconductor fin, respectively. The first source/drain epitaxy structure has a round surface. The first dielectric fin sidewall structure and the second dielectric fin sidewall structure are on opposite sides of the first source/drain epitaxy structure. The round surface of the first source/drain epitaxy structure is directly above the first dielectric fin sidewall structure.

Abstract: A method includes: providing a first gate electrode over the substrate; forming a first pair of spacers on two sides of the first gate electrode; removing the first gate electrode to form a first trench between the first pair of spacers; depositing a dielectric layer in the first trench; depositing a first layer over the dielectric layer; removing the first layer from the first trench; and depositing a work function layer over the dielectric layer in the first trench.

Abstract: Systems and methods of the present disclosure relate to calibration of a resistivity tool. A method for in-situ calibration of a resistivity logging tool, comprises transmitting signals with transmitters of the resistivity logging tool; measuring voltages at two or more receivers located at different distances to the transmitters of the resistivity logging tool; decoupling two or more sets of multi-component tensors at two or more receivers based on the measured voltages; calculating a ratio signal from two or more sets of multi-component tensors; obtaining an apparent resistivity based on the ratio signal; simulating a dipole response tensor at the first receiver based on the apparent resistivity; comparing the first set of multi-component tensor with the dipole response tensor to acquire an in-situ calibration factor; and applying the in-situ calibration factor to multi-components for an inversion input.

Abstract: Systems and methods of the present disclosure relate to calibration of resistivity logging tool. A method to calibrate a resistivity logging tool comprises disposing the resistivity logging tool into a formation; acquiring a signal at each logging point with the resistivity logging tool; assuming a formation model for a first set of continuous logging points in the formation; inverting all of the signals for unknown model parameters of the formation model, wherein the formation model is the same for all of the continuous logging points in the first set; assigning at least one calibration coefficient to each type of signal, wherein the calibration coefficients are the same for the first set; and building an unknown vector that includes the unknown model parameters and the calibration coefficients, to calibrate the resistivity logging tool.

Abstract: A method for manufacturing a semiconductor device includes etching a substrate to form a semiconductor fin. An isolation structure is formed above the substrate and laterally surrounds the semiconductor fin. A fin sidewall structure is formed above the isolation structure and on a sidewall of the semiconductor fin. The semiconductor fin is recessed to expose an inner sidewall of the fin sidewall structure. A source/drain epitaxial structure is grown on the recessed semiconductor fin.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. A sacrificial gate layer is removed to form a gate trench exposing a sacrificial dielectric layer. An ion implantation is performed to a portion of a substrate covered by the sacrificial dielectric layer in the gate trench. The sacrificial dielectric layer is removed to expose the substrate from the gate trench. An interfacial layer is formed over the substrate in the gate trench. A metal gate structure is formed over the interfacial layer in the gate trench.

Abstract: Systems and methods of the present disclosure relate to calibration of a resistivity tool. A calibration method comprises deploying a transmitter in a known formation with a known resistivity property with a physical tilted angle ? relative to a longitudinal axis of the tool; deploying receivers in the known formation, wherein a physical tilted angle of a first receiver is ? relative to the longitudinal axis of the tool, and wherein a physical tilted angle of a second receiver is ??, relative to the longitudinal axis of the tool; transmitting signals with the transmitter and measuring the signals at the receivers; combining measurements at two receivers with respect to a transmitter signal in the known formation; producing synthetic responses of the tool in the known formation using forward modeling; and calculating an effective tilted angle ?? from real measurements and the synthetic responses.

Abstract: Present disclosure provides a semiconductor structure, including a semiconductor fin having a first portion and a second portion over the first portion, a first conductive region abutting a first lateral surface of the first portion and a first lateral surface of the second portion, a metal gate having a bottom portion and an upper portion, the bottom portion being between the first portion and the second portion of the semiconductor fin, and the upper portion being over the second portion of the semiconductor fin, and a first spacer between the bottom portion of the metal gate and the first conductive region. A method for manufacturing the semiconductor structure described herein is also provided.

Abstract: A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.