Abstract: A method of generating masks for making an integrated circuit includes determining if a coupling capacitance value of a conductive path of a first and second groups of conductive paths of the integrated circuit is greater than a predetermined threshold value. The determination is performed based on at least a resistance-capacitance extraction result of the conductive path and a predetermined level of mask misalignment. The layout patterns are modified to increase an overall vertical distance between the first group of conductive paths and the second group of conductive paths if the coupling capacitance value is greater than the predetermined threshold value.

Abstract: A method of designing a semiconductor device is performed by at least one processor. In the method, a first environment temperature for a first substrate is determined based on an operational temperature of a second substrate, the first and second substrates stacked one upon another in the semiconductor device. An operation of at least one first circuit element in the first substrate is simulated based on the first environment temperature.

Abstract: A method of designing a fin field effect transistor (FinFET)-based circuit includes designing, using a processor, a first circuit schematic design based on a performance specification, the first circuit schematic design is free of artificial elements, wherein the artificial elements are used to simulate electrical performance of the FinFET-based circuit. The method further includes modifying, using the processor, at least one device within the first circuit schematic design to form a second circuit schematic design taking the artificial elements into consideration. The method further includes performing a pre-layout simulation using the second circuit schematic and taking the artificial elements into consideration.

Abstract: The present disclosure relates to a method and apparatus for forming a multiple patterning lithograph (MPL) compliant integrated circuit layout by operating a construction validation check on unassembled IC cells to enforce design restrictions that prevent MPL conflicts after assembly. In some embodiments, the method is performed by generating a plurality of unassembled integrated circuit (IC) cells having a multiple patterning design layer. A construction validation check is performed on the unassembled IC cells to identify violating IC cells having shapes disposed in patterns comprising potential multiple patterning coloring conflicts. Design shapes within a violating IC cell are adjusted to achieve a plurality of violation free IC cells. The plurality of violation free IC cells are then assembled to form an MPL compliant IC layout. Since the MPL compliant IC layout is free of coloring conflicts, a decomposition algorithm can be operated without performing a post assembly color conflict check.

Abstract: A non-transitory, computer readable storage medium is encoded with computer program instructions, such that, when the computer program instructions are executed by a computer, the computer performs a method. The method generates mask assignment information for forming a plurality of patterns on a layer of an integrated circuit (IC) by multipatterning. The mask assignment information includes, for each of the plurality of patterns, a mask assignment identifying which of a plurality of masks is to be used to form that pattern, and a mask assignment lock state for that pattern. User inputs setting the mask assignment of at least one of the plurality of patterns, and its mask assignment lock state are received. A new mask assignment is generated for each of the plurality of patterns having an “unlocked” mask assignment lock state.

Abstract: An apparatus comprises two n-type metal oxide semiconductor (MOS) devices formed next to each other. Each n-type MOS device further includes a pair of face-to-face diodes formed in an isolation ring. A method of modeling the apparatus comprises reusing four-terminal MOS device models in standard cell libraries and combining the four-terminal MOS device model and the isolation ring model into a 4T MOS plus isolation ring model. The method of modeling the apparatus further comprises adding a dummy device between a body contact of the first n-type MOS device and a body contact of the second n-type MOS device.

Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.

Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.

Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

Abstract: A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

Abstract: A method for analyzing an IC design, comprises: using a computer implemented electronic design automation tool to perform a parasitic RC extraction for a layout of the IC design, the parasitic RC extraction outputting for each of a plurality of routing paths, a nominal capacitive coupling, a minimum capacitive coupling and a maximum capacitive coupling, where the minimum and maximum capacitive couplings correspond to circuit patterning in the presence of double patterning mask misalignments; and performing one of a setup time analysis or a hold time analysis of the IC design using a computer implemented static timing analysis tool. For a given flip-flop having a launch path and a capture path, the setup or hold time analyses is performed using the minimum capacitive coupling for one of the launch and capture paths and the maximum capacitive coupling for the other of the launch and capture paths.

Abstract: A method of generating a simulation model of a predefined fabrication process according to a sample conductive feature includes receiving a geometry configuration and layout design of the conductive feature. A circuit-level simulation model of the sample conductive feature based on the geometry configuration of the sample conductive feature is generated. A hardware processor converts the circuit-level simulation model of the sample conductive feature into at least a first layout bias rule corresponding to a first set of predetermined criteria of the layout design and a second layout bias rule, different from the first layout bias rule, corresponding to a second set of predetermined criteria of the layout design.

Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.

Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.

Abstract: A semiconductor device design system comprising at least one processor is configured to define a resistance-capacitance (RC) extraction tool for determining a distance between first and second through-semiconductor-vias extracted from a layout of a semiconductor device. The semiconductor device has a semiconductor substrate and the first and second through-semiconductor-vias in the semiconductor substrate. The semiconductor device design system comprising the at least one processor is also configured to extract parasitic parameters of a coupling in the semiconductor substrate based on the distance determined by the RC extraction tool and a model of the coupling included in a simulation tool.

Abstract: A method for circuit design includes a parasitic aware library embedded with one or more parameterized cells. The parasitic aware library is used to insert nets representing some but not all parasitic effects of a circuit into a circuit schematic enabling a single circuit schematic to be used for simulation of the circuit, parasitic verification of the circuit and LVS (Layout Versus Schematic) check. Only the single circuit schematic is required for the circuit design process and to form a mask set. Critical paths of the single circuit schematic are identified and parasitic effects are extracted and inserted into the schematic, enabling a pre-estimation of parasitic verification to be carried out and the LVS check to be carried out using a circuit schematic with some parasitic effects prior to the post-layout simulation in which all parasitic components of the layout are included.

Abstract: A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule.

Abstract: A method includes selecting a process corner, determining model parameters for forming an integrated circuit, and generating a file using the model parameters for the process corner. The generating the file is performed using a computer. The file includes at least two of a first capacitance table, a second capacitance table, and a third capacitance table. The first capacitance table stores greatest parasitic capacitances between layout patterns of the integrated circuit when lithography masks including the layout patterns shift relative to each other. The second capacitance table stores smallest parasitic capacitances between the layout patterns when the lithography masks shift relative to each other. The third capacitance table stores nominal parasitic capacitances between the layout patterns when the lithography masks do not shift relative to each other.

Abstract: The present disclosure relates to an apparatus and method to generate a device library, along with layout versus schematic (LVS) and parasitic extraction set-up files for connecting with official tools of a design window supported by a process design kit (PDK). The device library comprises passive devices which can be utilized at any point in an end-to-end design flow from pre-layout verification to post-layout verification of an integrated circuit design. The device library allows for a single schematic view for pre-layout verification but also post-layout verification, thus allowing for pole or pin comparison, and prevents double-counting of parasitic effects from passive design elements by directly instantiating a device from the device library for a verification step. An LVS and parasitic extraction graphical user interface (GUI) allows for incorporation of the generated device library into a pre-existing PDK without any modification to the PDK. Other devices and methods are also disclosed.

Abstract: Methods are disclosed of modifying an integrated circuit (IC) design that utilizes multiple patterning technology (MPT). The methods include configuring a first layout of an integrated circuit, having at least one layer with features to be formed utilizing fabrication by at least two masks. The at least one layer includes a plurality of active cells and a plurality of spare cells. A second layout is configured to re-route the spare cells and active cells, wherein the re-routing utilizes at least a portion of the plurality of spare cells. Fewer than all of the at least two masks are replaced to configure the second layout.