Patents by Inventor Yi-Kan Cheng
Yi-Kan Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8255837Abstract: A method of designing a double patterning mask set for a layout of a chip includes designing standard cells. In each of the standard cells, all left-boundary patterns are assigned with one of a first indicator and a second indicator, and all right-boundary patterns are assigned with an additional one of the first indicator and the second indicator. The method further includes placing the standard cells in a row of the layout of the chip. Starting from one of the standard cells in the row, indicator changes to the standard cells are propagated throughout the row. All patterns in the standard cells having the first indicator are transferred to a first mask of the double patterning mask set. All patterns in the standard cells having the second indicator are transferred to a second mask of the double patterning mask set.Type: GrantFiled: November 12, 2009Date of Patent: August 28, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Yi-Kan Cheng, Yuan-Te Hou, Yung-Chin Hou, Li-Chun Tien
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Patent number: 8252489Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift. The step of simulating the worst-case performance includes calculating capacitance values corresponding to mask shifts, and the capacitance values are calculated using a high-order equation or a piecewise equation.Type: GrantFiled: June 24, 2011Date of Patent: August 28, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Chung-Hsing Wang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng
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Publication number: 20120210279Abstract: Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.Type: ApplicationFiled: February 15, 2011Publication date: August 16, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Chang HSU, Wen-Ju YANG, Hsiao-Shu CHAO, Yi-Kan CHENG, Lee-Chung LU
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Patent number: 8245174Abstract: A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC.Type: GrantFiled: August 27, 2009Date of Patent: August 14, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Kan Cheng, Ru-Gun Liu, Lee-Chung Lu
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Patent number: 8239806Abstract: A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.Type: GrantFiled: December 30, 2009Date of Patent: August 7, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Yu Chen, Yuan-Te Hou, Gwan Sin Chang, Wen-Ju Yang, Zhe-Wei Jiang, Yi-Kan Cheng, Lee-Chung Lu
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Patent number: 8214773Abstract: A method of forming integrated circuits for a wafer includes providing an E-Beam direct write (EBDW) system. A grid is generated for the wafer, wherein the grid includes grid lines. An integrated circuit is laid out for the wafer, wherein substantially no sensitive features in the integrated circuit cross the grid lines of the grid. An EBDW is performed on the wafer using the EBDW system.Type: GrantFiled: November 12, 2009Date of Patent: July 3, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Yi-Kan Cheng, Ru-Gun Liu, Chih-Ming Lai
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Patent number: 8201111Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.Type: GrantFiled: August 2, 2011Date of Patent: June 12, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Yi-Kan Cheng, Chung-Kai Lin, Hsiao-Shu Chao, Ping-Heng Yeh, Min-Hong Wu, Yao-Ching Ku, Tsong-Hua Ou
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Patent number: 8136168Abstract: An encryption and decryption interface for integrated circuit (IC) design with design-for-manufacturing (DFM). The interface includes a decryption module embedded in an IC design tool; an encrypted DFM data provided to an IC designer authorized for utilizing the encrypted DFM data; and a private key provided to the IC designer for decrypting the encrypted DFM data in the IC design tool.Type: GrantFiled: March 16, 2007Date of Patent: March 13, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Kan Cheng, Gwan Sin Chang, Jill Liu, Hsiao-Shu Chiao
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Publication number: 20120052422Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.Type: ApplicationFiled: August 31, 2010Publication date: March 1, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Yi-Kan Cheng, Hsiao-Shu Chao, Ke-Ying Su, Cheng-Hung Yeh, Dian-Hau Chen, Ru-Gun Liu, Wen-Chun Huang
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Publication number: 20120054696Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift. The step of simulating the worst-case performance includes calculating capacitance values corresponding to mask shifts, and the capacitance values are calculated using a high-order equation or a piecewise equation.Type: ApplicationFiled: June 24, 2011Publication date: March 1, 2012Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ke-Ying Su, Chung-Hsing Wang, Jui-Feng Kuan, Hsiao-Shu Chao, Yi-Kan Cheng
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Patent number: 8119310Abstract: A method includes providing a layout of an integrated circuit design, and generating a plurality of double patterning decompositions from the layout, with each of the plurality of double patterning decompositions including patterns separated to a first mask and a second mask of a double patterning mask set. A maximum shift between the first and the second masks is determined, wherein the maximum shift is a maximum expected mask shift in a manufacturing process for implementing the layout on a wafer. For each of the plurality of double patterning decompositions, a worst-case performance value is simulated using mask shifts within a range defined by the maximum shift.Type: GrantFiled: August 31, 2010Date of Patent: February 21, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Yi-Kan Cheng, Hsiao-Shu Chao, Ke-Ying Su, Cheng-Hung Yeh, Dian-Hau Chen, Ru-Gun Liu, Wen-Chun Huang
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Publication number: 20110289466Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.Type: ApplicationFiled: August 2, 2011Publication date: November 24, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Chin Hou, Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Yi-Kan Cheng, Chung-Kai Lin, Hsiao-Shu Chao, Ping-Heng Yeh, Min-Hong Wu, Yao-Ching Ku, Tsong-Hua Ou
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Patent number: 8037575Abstract: An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.Type: GrantFiled: September 16, 2008Date of Patent: October 18, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Chou Cheng, Chih-Ming Lai, Ru-Gun Liu, Tsong-Hua Ou, Min-Hong Wu, Yih-Yuh Doong, Hsiao-Shu Chao, Yi-Kan Cheng, Yao-Ching Ku, Cliff Hou
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Patent number: 8001494Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.Type: GrantFiled: October 13, 2008Date of Patent: August 16, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Yi-Kan Cheng, Chung-Kai Lin, Hsiao-Shu Chao, Ping-Heng Yeh, Min-Hong Wu, Yao-Ching Ku, Tsong-Hua Ou
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Publication number: 20110193234Abstract: A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.Type: ApplicationFiled: February 9, 2010Publication date: August 11, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huang-Yu Chen, Yuan-Te Hou, Fung Song Lee, Wen-Ju Yang, Gwan Sin Chang, Yi-Kan Cheng, Li-Chun Tien, Lee-Chung Lu
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Publication number: 20110119648Abstract: A method includes receiving an identification of a plurality of circuit components to be included in an IC layout. Data are generated representing a first pattern to connect two of the circuit components. The first pattern has a plurality of segments. At least two of the segments have lengthwise directions perpendicular to each other. At least one pattern-free region is reserved adjacent to at least one of the at least two segments. Data are generated representing one or more additional patterns near the first pattern. None of the additional patterns is formed in the pattern-free region. The first pattern and the additional patterns form a double-patterning compliant set of patterns. The double-patterning compliant set of patterns are output to a machine readable storage medium to be read by a system for controlling a process to fabricate a pair of masks for patterning a semiconductor substrate using double patterning technology.Type: ApplicationFiled: December 30, 2009Publication date: May 19, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Huang-Yu Chen, Yuan-Te Hou, Gwan Sin Chang, Wen-Ju Yang, Zhe-Wei Jiang, Yi-Kan Cheng, Lee-Chung Lu
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Publication number: 20110072405Abstract: In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed.Type: ApplicationFiled: July 7, 2010Publication date: March 24, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huang-Yu Chen, Ho Che Yu, Chung-Hsing Wang, Hsiao-Shu Chao, Yi-Kan Cheng, Lee-Chung Lu
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Publication number: 20110035717Abstract: An embodiment of the present invention is a computer program product for providing an adjusted electronic representation of an integrated circuit layout. The computer program product has a medium with a computer program embodied thereon. Further, the computer program comprises computer program code for providing full node cells from a full node netlist, computer program code for scaling the full node cells to provide shrink node cells, computer program code for providing a timing performance of the full node cells and the shrink node cells, computer program code for comparing the timing performance of the full node cells to the timing performance of the shrink node cells, and computer program code for providing a first netlist.Type: ApplicationFiled: July 29, 2010Publication date: February 10, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lee-Chung Lu, Yi-Kan Cheng, Chung-Hsing Wang, Chen-Fu Alex Huang, Hsiao-Shu Chao, Chin-Yu Chiang, Ho Che Yu, Chih Sheng Tsai, Shu Yi Ying
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Publication number: 20110023002Abstract: A method includes receiving an identification of a plurality of cells to be included in an integrated circuit (IC) layout, including a list of pairs of cells within the plurality of cells to be connected to each other. First routing paths are identified, to connect a maximum number of the pairs of cells using one-dimensional (1-D) routing between cells within those pairs of cells. Second routing paths are selected from a predetermined set of two-dimensional (2-D) routing patterns to connect any of the pairs of cells which cannot be connected by 1-D routing. The first and second routing paths are output to a machine readable storage medium to be read by a control system for controlling a semiconductor fabrication process to fabricate the IC.Type: ApplicationFiled: August 27, 2009Publication date: January 27, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Kan Cheng, Ru-Gun Liu, Lee-Chung Lu
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Publication number: 20100281446Abstract: Integrated circuit libraries include a first standard cell having a first left boundary and a first right boundary, and a second standard cell having a second left boundary and a second right boundary. The first standard cell and the second standard cell are of a same cell variant. A first active region in the first standard cell has a different length of diffusion than a second active region in the second standard cell. The first active region and the second active region are corresponding active regions represented by a same component of a same circuit diagram representing both the first standard cell and the second standard cell.Type: ApplicationFiled: February 18, 2010Publication date: November 4, 2010Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Lee-Chung Lu, Li-Chun Tien, Yi-Kan Cheng, Chun-Hui Tai, Ta-Pen Guo, Yuan-Te Hou