Patents by Inventor Yi MIN

Yi MIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12199047
    Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: January 14, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Po-Yuan Su
  • Publication number: 20250010432
    Abstract: A ratchet wrench includes a head, a toothed wheel, a pawl and a switch. The head includes two bores in communication with a pothole in communication with a chamber via a channel. The channel includes a broad section between two tapered sections. The toothed wheel is rotatable in the chamber. The switch is pivotable in the pothole and includes a tunnel with a first end in communication with the broad section of the channel and a second end in communication with the pothole. A spring is compressed between a detent and a ball. The detent includes an end connected to the pawl and another end movable in the tunnel. The ball includes a portion in the tunnel and another portion insertable in a selected one of the bores when the detent moves the pawl into a corresponding one of the tapered sections of the channel.
    Type: Application
    Filed: July 6, 2023
    Publication date: January 9, 2025
    Inventor: Yi-Min Li
  • Patent number: 12176291
    Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: December 24, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Shuai-Lin Liu
  • Publication number: 20240421026
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure, a heat conduction layer is formed on the electronic element, and a heat dissipation member having a recess portion is disposed on the heat conduction layer to cover the electronic element. Therefore, the arrangement of the recess portion can buffer the flow of the heat conduction layer to facilitate the formation of an intermetallic structure with sufficient thickness between the heat dissipation member and the electronic element, and the heat dissipation effect of the electronic element can meet expectations.
    Type: Application
    Filed: August 11, 2023
    Publication date: December 19, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chiu-Ling CHEN, Shuai-Lin LIU, Pin-Jing SU, Yi-Min FU, Lung-Yuan WANG
  • Publication number: 20240413749
    Abstract: A multilevel buck converter includes a plurality of switches, an inductor, a flying capacitor, and a control circuit. The plurality of switches are coupled between an input terminal and a ground. The input terminal has an input voltage. The inductor is coupled between the plurality of switches and an output terminal for generating an inductor-current signal. The flying capacitor is coupled to the plurality of switches for generating a flying capacitor voltage. The control circuit is coupled to the output terminal and the plurality of switches for generating a plurality of switching signals according a feedback voltage and the inductor-current signal. The control circuit operates in a valley current mode with dual slope compensation.
    Type: Application
    Filed: August 31, 2023
    Publication date: December 12, 2024
    Inventors: Kuo-Chi Liu, Ta-Yung Yang, Yi-Min Shiu
  • Patent number: 12161199
    Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: December 10, 2024
    Assignee: NIKE, Inc.
    Inventors: Chun-Chieh Chen, Yi-Min Chen, Chia-Hung Lin, Hsien-Kuang Wu, Hung-Yu Wu
  • Publication number: 20240395937
    Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Yi-Min Huang, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20240379590
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure with a circuit layer, a first encapsulating layer and a second encapsulating layer are formed on the carrier structure to cover the electronic element, a first antenna layer is formed on the first encapsulating layer, and a second antenna layer communicatively connected to the first antenna layer is formed on the second encapsulating layer. Therefore, the thickness of the first encapsulating layer is used to control the resonance distance of the antenna frequency so as to generate better resonance effect, and the distance between the first antenna layer and the second antenna layer is controlled by the thickness of the second encapsulating layer to increase the bandwidth of the antenna.
    Type: Application
    Filed: August 11, 2023
    Publication date: November 14, 2024
    Inventors: Chia-Chu LAI, Yi-Min FU, Chien-Sheng CHEN
  • Patent number: 12142681
    Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Min Huang, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20240371721
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a heat sink with an opening is disposed on an electronic component of a carrier structure, a heat dissipation material is formed in the opening, and a heat dissipation lid is disposed on the opening to cover the heat dissipation material, such that the problem of insufficient heat dissipation due to the loss of the heat dissipation material can be prevented from occurring to the electronic component.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 7, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min FU, Chi-Ching HO, Chao-Chiang PU, Yu-Po WANG
  • Publication number: 20240363680
    Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hong-Yang CHEN, Tian Sheng LIN, Yi-Cheng CHIU, Hung-Chou LIN, Yi-Min CHEN, Kuo-Ming WU, Chiu-Hua CHUNG
  • Publication number: 20240363545
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a full-panel wafer is provided and includes a plurality of electronic bodies arranged in an array at intervals, a plurality of trenches are formed across the electronic bodies along a first direction on the full-panel wafer, so that the trenches on a single electronic body are arranged parallel to each other at interval and along a second direction perpendicular to the first direction. Then, in a singulation process, any trench can be selected for cutting to obtain a plurality of electronic elements of a required size. Finally, each of the electronic elements is disposed on a packaging region of a carrier structure, so that each of the electronic elements is electrically connected to at least a portion of electrical contact pads in the packaging region.
    Type: Application
    Filed: July 14, 2023
    Publication date: October 31, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Che-Yu LEE, Chi-Ching HO, Chao-Chiang PU, Yi-Min FU, Po-Yuan SU
  • Publication number: 20240332065
    Abstract: The present disclosure relates to a method of forming an interconnect structure that eliminates a separate deep via patterning process to simplify the fabrication process. In some embodiments, a first dielectric layer is formed over a first metal line and patterned to form a through-hole exposing a first contact region of the first metal line. A second dielectric layer is deposited and patterned to form a first via-hole connecting to the through-hole and a second via-hole exposing a second contact region of the second metal line from a layout view. A first via is formed on the first contact region extending to a first upper surface of the second dielectric layer, and a second via is formed on the second contact region extending to a second upper surface of the second dielectric layer.
    Type: Application
    Filed: March 28, 2023
    Publication date: October 3, 2024
    Inventors: Yao-Hong You, Dah-Chuen Ho, Kuo-Ming Wu, Ying-De Chen, Yi-Min Chen
  • Publication number: 20240321079
    Abstract: A hand tool operation management apparatus includes a hand-tool-state sensing unit, a wireless communication unit, a microcontroller, and a warning unit. A wireless apparatus generates a predetermined value wireless signal including a plurality of predetermined values and wirelessly transmits the predetermined value wireless signal to the wireless communication unit. The wireless communication unit converts the predetermined value wireless signal into a predetermined value wired signal and transmits the predetermined value wired signal to the microcontroller. The hand-tool-state sensing unit senses a state of a hand tool to obtain a hand-tool-state value and transmits the hand-tool-state value to the microcontroller. The microcontroller compares the hand-tool-state value with the predetermined values.
    Type: Application
    Filed: March 20, 2024
    Publication date: September 26, 2024
    Inventors: Yi-Min WU, Victoria WU
  • Patent number: 12099963
    Abstract: An example operation may include one or more of acquiring, by a processor node, identification data from an asset producer node over a supply blockchain, generating, by the processor node, a unique identifier (ID) for the asset producer node, and executing a smart contract to: map the ID to the identification data and provide an entitlement to the asset producer node to a plurality of supplier nodes based on the mapped ID.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: September 24, 2024
    Assignee: International Business Machines Corporation
    Inventors: Nathan Robert Barry, Sheela Shetty, Yi-Min Chee
  • Publication number: 20240314960
    Abstract: A circuit board is adapted for inserting an expansion card with an electrical contact part, a non-electrical convex part, and a positioning part. The circuit board includes a board body, a slot, a release structure, and a transmission mechanism. The slot is disposed on the board body and includes a socket, a connecting end, and an outer surface. The socket is adapted for the electrical contact part to be inserted. The release structure is movably disposed at the connecting end and includes a limiting part. The transmission mechanism is disposed in the socket, adjacent to the connecting end, or adjacent to the outer surface. The transmission mechanism includes a driving member and a linking member. The driving member is adapted for contacting the electrical contact part, the non-electrical convex part, or the positioning part. The linking member is disposed between the driving member and the release structure.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 19, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Wei-Chia Liao, Wen-Ting Yu, Chin-Chuan Wu, Yi-Min Hsu
  • Publication number: 20240305034
    Abstract: An electrical connector assembly includes: an insulative housing; a terminal module including a first terminal module and a second terminal module stacked with each other in a vertical direction; and a cable electrically connected to the terminal module; wherein the first terminal module includes a first row of terminals and a first insulating member holding the first row of terminals, the second terminal module includes a second row of terminals and a second insulating member holding the second row of terminals, each of the first row of terminals and the second row of terminals include a sideband terminal area and high-speed terminal areas located on the two sides of the sideband terminal area, the cable is mechanically and electrically connected to the high-speed terminal area, and the first row of terminals and the second row of terminals have same structure.
    Type: Application
    Filed: March 4, 2024
    Publication date: September 12, 2024
    Inventors: CHUN-HSIUNG HSU, Yi-Min Hsu
  • Publication number: 20240305024
    Abstract: A contact assembly for an electrical connector including: a row of contacts having plural contacting portions and plural mounting portions; an insulator secured to the plural contacting portions and the plural mounting portions; and an upper ground plate and a lower ground plate surrounding the row of contacts, wherein a conductive element is provided to electrically connect the upper and lower ground plates and selected ones of the row of contacts, or at least one of the upper and lower ground plates integrally forms plural ground sections constituting part of the plural contacting portions of the row of contacts.
    Type: Application
    Filed: March 12, 2024
    Publication date: September 12, 2024
    Inventors: PATRICK R. CASHER, Terrance F. LITTLE, Chun-Hsiung HSU, Yi-Min HSU, Haozhe ZI
  • Publication number: 20240290701
    Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 29, 2024
    Inventors: Yi-Min FU, Chi-Ching HO, Cheng-Yu KANG, Yu-Po WANG
  • Publication number: 20240285070
    Abstract: A modular cabinet assembly has at least a first sub-cabinet and a second sub-cabinet. Each sub-cabinet includes a back board having at least two separate back board pieces that are pivotably connected to each other, a left side board pivotably connected to one of the at least two back board pieces, and a right side board pivotably connected to another of the at least two back board pieces. At least one shelf board having opposite ends is removably connected to the left side board and the right side board of either the first sub-cabinet or the second sub-cabinet. A first end board is connected to either an upper end of the first sub-cabinet or a lower end of the second sub-cabinet. A first connector removably connects the left side boards of the first and second sub-cabinets, and a second connector removably connects the right side boards of the first and second sub-cabinets.
    Type: Application
    Filed: May 5, 2024
    Publication date: August 29, 2024
    Applicant: Seville Classics Inc.
    Inventors: Gary M. Lim, Yi Min Li