Patents by Inventor Yi MIN

Yi MIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11877559
    Abstract: The present invention discloses a foldable suction cup-type pet hammock, which comprises at least one fixed component and a bedstead, wherein the back of the fixed component is provided with at least one suction cup; the bedstead is rotatably connected with the fixed component and comprises at least one L-shaped pipe; the bedstead has a first position and a second position relative to the fixed component; the fixed component is provided with a limiting component to keep the bedstead in the first position or the second position; and a mattress with a thickness is also arranged on the bedstead, and when a pet hammock is in the folded or unfolded state, the mattress has a relatively flat surface.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: January 23, 2024
    Inventor: Yi Min
  • Patent number: 11876890
    Abstract: An example operation may include one or more of generating, by a processor node, an identifier (ID) for an asset producer node, mapping, by the processor node, the ID to an identity of an asset producer node, receiving, by the processor node, a request from a supplier node from a plurality of supplier nodes for the asset producer node to be added to a supply blockchain, and providing entitlements to the plurality of the supplier nodes based on the mapped ID.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: January 16, 2024
    Assignee: International Business Machines Corporation
    Inventors: Nathan Robert Barry, Sheela Shetty, Yi-Min Chee
  • Publication number: 20240006842
    Abstract: A package structure is provided. The package structure includes a substrate, a frame structure, and a lens portion. The frame structure is disposed on the substrate. A sidewall of the frame structure has multiple lamination traces thereon. The lens portion covers the substrate. The frame structure has a through hole passing through the sidewall, and the through hole includes an edge, and a portion of the lamination traces overlaps the edge of the through hole.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 4, 2024
    Inventors: Meng Hsin KUO, Ming-Jing LEE, Yi-Min CHEN
  • Patent number: 11862675
    Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Karthick Murukesan, Wen-Chih Chiang, Chun Lin Tsai, Ker-Hsiao Huo, Kuo-Ming Wu, Po-Chih Chen, Ru-Yi Su, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Yi-Cheng Chiu
  • Publication number: 20230420882
    Abstract: An electrical connector assembly includes: an insulative housing forming a front mating slot and a rear receiving space; a contact module received in the insulative housing and including an upper part and a lower part stacked with each other, each of the upper part and the lower part including a differential pair contact module having an insulator and a plurality of differential pair contact fixed in the insulator, each of the differential pair contact having a mating portion and a tail portion opposite to the mating portion; and a sideband contact module comprising sideband contacts, wherein the differential pair contacts and the sideband contacts are fixed to the insulator in different ways.
    Type: Application
    Filed: June 20, 2023
    Publication date: December 28, 2023
    Inventors: CHUN-HSIUNG HSU, YI-MIN HSU
  • Patent number: 11854811
    Abstract: A finFET device and methods of forming are provided. The method includes etching recesses in a substrate on opposite sides of a gate stack. The method also includes epitaxially growing a source/drain region in each recess, where each of the source/drain regions includes a capping layer along a top surface of the respective source/drain region, and where a concentration of a first material in each source/drain region is highest at an interface of the capping layer and an underlying epitaxy layer. The method also includes depositing a plurality of metal layers overlying and contacting each of the source/drain regions. The method also includes performing an anneal, where after the anneal a metal silicide region is formed in each of the source/drain regions, where each metal silicide region extends through the capping layer and terminates at the interface of the capping layer and the underlying epitaxy layer.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Min Huang, Huai-Tei Yang, Shih-Chieh Chang
  • Publication number: 20230409791
    Abstract: The present disclosure describes a system and method for determining a function for a quality of results (QoR) for a circuit design. The method includes receiving a circuit design that includes a first node, a second node, and a connection between the first node and the second node in a design space, placing an array of points within the design space, sampling first field values of the circuit design at each point of the array of points, and determining a first sampled function based on the first field values. The method includes moving the array of points within the design space, sampling second field values of the circuit design at each point of the array of points, determining a second sampled function based on the second field values, and determining a function based on the first and second sampled functions. The function produces a QoR for the circuit design.
    Type: Application
    Filed: June 20, 2023
    Publication date: December 21, 2023
    Inventors: Xiang GAO, Yi-Min JIANG, Manish SHARMA
  • Publication number: 20230410878
    Abstract: A memory system includes a memory device and a processing device coupled to the memory device. The processing device receives a plurality of codewords; determines that one or more codewords of the plurality of codewords are corrupt; selects a first read voltage associated with the one or more codewords, such that the first read voltage is based on a second read voltage utilized for reading the one or more codewords in a previous read operation; and applies the first read voltage to a set of memory cells storing the one or more corrupted codewords.
    Type: Application
    Filed: September 5, 2023
    Publication date: December 21, 2023
    Inventors: Yi-Min Lin, Fangfang Zhu, Chih-Kuo Kao
  • Publication number: 20230397696
    Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.
    Type: Application
    Filed: August 24, 2023
    Publication date: December 14, 2023
    Inventors: Chun-Chieh Chen, Yi-Min Chen, Chia-Hung Lin, Hsien-Kuang Wu, Hung-Yu Wu
  • Patent number: 11843086
    Abstract: A semiconductor structure includes a substrate, a plurality of micro semiconductor devices and a fixing structure. The micro semiconductor devices are disposed on the substrate. The fixing structure is disposed between the substrate and the micro semiconductor devices. The fixing structure includes a plurality of conductive layers and a plurality of supporting layers. The conductive layers are disposed on the lower surfaces of the micro semiconductor devices. The supporting layers are connected to the conductive layers and the substrate. The material of each of the conductive layers is different from the material of each of the supporting layers.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: December 12, 2023
    Assignee: PLAYNITRIDE DISPLAY CO., LTD.
    Inventors: Shiang-Ning Yang, Chih-Ling Wu, Yi-Min Su, Bo-Wei Wu
  • Patent number: 11825916
    Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: November 28, 2023
    Assignee: NIKE, Inc.
    Inventors: Chun-Chieh Chen, Yi-Min Chen, Chia-Hung Lin, Hsien-Kuang Wu, Hung-Yu Wu
  • Publication number: 20230378072
    Abstract: An electronic package is provided, in which a plurality of electronic elements are disposed on a plurality of carrier structures, and at least one bridging element is disposed between at least two of the carrier structures to electrically bridge the two carrier structures. Therefore, when there is a need to increase the function of the electronic package, only one electronic element is arranged on a single carrier structure, and there is no need to increase the panel area of the carrier structure, so as to facilitate the control of the panel area of the carrier structure and avoid warpage of the carrier structure due to the oversized panel.
    Type: Application
    Filed: July 5, 2022
    Publication date: November 23, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Shuai-Lin Liu, Nai-Hao Kao, Chao-Chiang Pu, Yi-Min Fu, Yu-Po Wang
  • Patent number: 11821782
    Abstract: The disclosure relates to a load cell including an elastic element, at least one strain gauge and a limitation element. The elastic element includes a first end portion, a second end portion and a deformation region. The first end portion and the second end portion are arranged along an axial direction and opposed to each other. The deformation region is located between the first end portion and the second end portion. The at least one strain gauge is disposed in the deformation region. When a force is exerted on the first end portion in a first direction, the deformation region is deformed to drive the at least one strain gauge to change shape, so that the force is measured and standardized under a specific range. The limitation element is connected to the elastic element. A gap is formed between the limitation element and the elastic element.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: November 21, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yu-Xian Huang, Yi-Min Liang, Chieh-Huang Lu
  • Patent number: 11819090
    Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: November 21, 2023
    Assignee: NIKE, Inc.
    Inventors: Chun-Chieh Chen, Yi-Min Chen, Chia-Hung Lin, Hsien-Kuang Wu, Hung-Yu Wu
  • Publication number: 20230361024
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.
    Type: Application
    Filed: July 18, 2023
    Publication date: November 9, 2023
    Inventors: Te-Hsien Hsieh, Yu-Hsing Chang, Yi-Min Chen
  • Publication number: 20230343816
    Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.
    Type: Application
    Filed: June 28, 2023
    Publication date: October 26, 2023
    Inventors: Hong-Yang CHEN, Tian Sheng Lin, Yi-Cheng Chiu, Hung-Chou Lin, Yi-Min Chen, Kuo-Ming Wu, Chiu-Hua Chung
  • Patent number: 11798614
    Abstract: A system can include a memory devices and a processing device coupled with the memory devices. The processing device can receive a command and determine whether the command includes a value for a voltage associated with a read at the memory device. The processing device can also, responsive to the command failing to specify the value, select a second value, from multiple values, for the voltage associated with the read at the memory device based at on a duration subsequent to a previous write operation satisfying a threshold criterion. The processing device can also apply the voltage having the second value at memory cells of the memory device to determine a logic state for the memory cells.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: October 24, 2023
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Yi-Min Lin, Fangfang Zhu, Chih-Kuo Kao
  • Patent number: 11776901
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a conductive structure arranged within a substrate or a first dielectric layer. A first barrier layer is arranged on outermost sidewalls and a bottom surface of the conductive structure. A second barrier layer is arranged on outer surfaces of the first barrier layer. The second barrier layer separates the first barrier layer from the substrate or the first dielectric layer. A second dielectric layer is arranged over the substrate or the first dielectric layer. A via structure extends through the second dielectric layer, is arranged directly over topmost surfaces of the first and second barrier layers, and is electrically coupled to the conductive structure through the first and second barrier layers.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Hsien Hsieh, Yu-Hsing Chang, Yi-Min Chen
  • Patent number: 11772243
    Abstract: A ratchet screwdriver includes a direction-switching apparatus. The direction-switching apparatus includes a cylinder, a toothed wheel, two pawls, two springs and a connector. The cylinder includes a wheel-containing chamber in communication with two pawl-containing chambers. The toothed wheel is inserted in the wheel-containing chamber. The pawls are respectively inserted in the pawl-containing chambers. Each of the springs is connected to one of the pawls in one of the pawl-containing chambers. The connector interconnects the springs so that at least one of the springs keeps at least one of the pawls engaged with the toothed wheel to allow the cylinder to rotate the toothed wheel in at least one of two directions.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: October 3, 2023
    Inventor: Yi-Min Li
  • Patent number: D1003534
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: October 31, 2023
    Inventor: Yi Min