Patents by Inventor Yi MIN

Yi MIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240363545
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a full-panel wafer is provided and includes a plurality of electronic bodies arranged in an array at intervals, a plurality of trenches are formed across the electronic bodies along a first direction on the full-panel wafer, so that the trenches on a single electronic body are arranged parallel to each other at interval and along a second direction perpendicular to the first direction. Then, in a singulation process, any trench can be selected for cutting to obtain a plurality of electronic elements of a required size. Finally, each of the electronic elements is disposed on a packaging region of a carrier structure, so that each of the electronic elements is electrically connected to at least a portion of electrical contact pads in the packaging region.
    Type: Application
    Filed: July 14, 2023
    Publication date: October 31, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Che-Yu LEE, Chi-Ching HO, Chao-Chiang PU, Yi-Min FU, Po-Yuan SU
  • Publication number: 20240332065
    Abstract: The present disclosure relates to a method of forming an interconnect structure that eliminates a separate deep via patterning process to simplify the fabrication process. In some embodiments, a first dielectric layer is formed over a first metal line and patterned to form a through-hole exposing a first contact region of the first metal line. A second dielectric layer is deposited and patterned to form a first via-hole connecting to the through-hole and a second via-hole exposing a second contact region of the second metal line from a layout view. A first via is formed on the first contact region extending to a first upper surface of the second dielectric layer, and a second via is formed on the second contact region extending to a second upper surface of the second dielectric layer.
    Type: Application
    Filed: March 28, 2023
    Publication date: October 3, 2024
    Inventors: Yao-Hong You, Dah-Chuen Ho, Kuo-Ming Wu, Ying-De Chen, Yi-Min Chen
  • Publication number: 20240321079
    Abstract: A hand tool operation management apparatus includes a hand-tool-state sensing unit, a wireless communication unit, a microcontroller, and a warning unit. A wireless apparatus generates a predetermined value wireless signal including a plurality of predetermined values and wirelessly transmits the predetermined value wireless signal to the wireless communication unit. The wireless communication unit converts the predetermined value wireless signal into a predetermined value wired signal and transmits the predetermined value wired signal to the microcontroller. The hand-tool-state sensing unit senses a state of a hand tool to obtain a hand-tool-state value and transmits the hand-tool-state value to the microcontroller. The microcontroller compares the hand-tool-state value with the predetermined values.
    Type: Application
    Filed: March 20, 2024
    Publication date: September 26, 2024
    Inventors: Yi-Min WU, Victoria WU
  • Patent number: 12099963
    Abstract: An example operation may include one or more of acquiring, by a processor node, identification data from an asset producer node over a supply blockchain, generating, by the processor node, a unique identifier (ID) for the asset producer node, and executing a smart contract to: map the ID to the identification data and provide an entitlement to the asset producer node to a plurality of supplier nodes based on the mapped ID.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: September 24, 2024
    Assignee: International Business Machines Corporation
    Inventors: Nathan Robert Barry, Sheela Shetty, Yi-Min Chee
  • Publication number: 20240314960
    Abstract: A circuit board is adapted for inserting an expansion card with an electrical contact part, a non-electrical convex part, and a positioning part. The circuit board includes a board body, a slot, a release structure, and a transmission mechanism. The slot is disposed on the board body and includes a socket, a connecting end, and an outer surface. The socket is adapted for the electrical contact part to be inserted. The release structure is movably disposed at the connecting end and includes a limiting part. The transmission mechanism is disposed in the socket, adjacent to the connecting end, or adjacent to the outer surface. The transmission mechanism includes a driving member and a linking member. The driving member is adapted for contacting the electrical contact part, the non-electrical convex part, or the positioning part. The linking member is disposed between the driving member and the release structure.
    Type: Application
    Filed: May 16, 2023
    Publication date: September 19, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Wei-Chia Liao, Wen-Ting Yu, Chin-Chuan Wu, Yi-Min Hsu
  • Publication number: 20240305034
    Abstract: An electrical connector assembly includes: an insulative housing; a terminal module including a first terminal module and a second terminal module stacked with each other in a vertical direction; and a cable electrically connected to the terminal module; wherein the first terminal module includes a first row of terminals and a first insulating member holding the first row of terminals, the second terminal module includes a second row of terminals and a second insulating member holding the second row of terminals, each of the first row of terminals and the second row of terminals include a sideband terminal area and high-speed terminal areas located on the two sides of the sideband terminal area, the cable is mechanically and electrically connected to the high-speed terminal area, and the first row of terminals and the second row of terminals have same structure.
    Type: Application
    Filed: March 4, 2024
    Publication date: September 12, 2024
    Inventors: CHUN-HSIUNG HSU, Yi-Min Hsu
  • Publication number: 20240305024
    Abstract: A contact assembly for an electrical connector including: a row of contacts having plural contacting portions and plural mounting portions; an insulator secured to the plural contacting portions and the plural mounting portions; and an upper ground plate and a lower ground plate surrounding the row of contacts, wherein a conductive element is provided to electrically connect the upper and lower ground plates and selected ones of the row of contacts, or at least one of the upper and lower ground plates integrally forms plural ground sections constituting part of the plural contacting portions of the row of contacts.
    Type: Application
    Filed: March 12, 2024
    Publication date: September 12, 2024
    Inventors: PATRICK R. CASHER, Terrance F. LITTLE, Chun-Hsiung HSU, Yi-Min HSU, Haozhe ZI
  • Publication number: 20240290701
    Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 29, 2024
    Inventors: Yi-Min FU, Chi-Ching HO, Cheng-Yu KANG, Yu-Po WANG
  • Publication number: 20240285070
    Abstract: A modular cabinet assembly has at least a first sub-cabinet and a second sub-cabinet. Each sub-cabinet includes a back board having at least two separate back board pieces that are pivotably connected to each other, a left side board pivotably connected to one of the at least two back board pieces, and a right side board pivotably connected to another of the at least two back board pieces. At least one shelf board having opposite ends is removably connected to the left side board and the right side board of either the first sub-cabinet or the second sub-cabinet. A first end board is connected to either an upper end of the first sub-cabinet or a lower end of the second sub-cabinet. A first connector removably connects the left side boards of the first and second sub-cabinets, and a second connector removably connects the right side boards of the first and second sub-cabinets.
    Type: Application
    Filed: May 5, 2024
    Publication date: August 29, 2024
    Applicant: Seville Classics Inc.
    Inventors: Gary M. Lim, Yi Min Li
  • Publication number: 20240283467
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Application
    Filed: April 22, 2024
    Publication date: August 22, 2024
    Inventors: Kyoung Lae CHO, Soo Jin KIM, Naveen KUMAR, Aman BHATIA, Yi-Min LIN, Chenrong XIONG, Fan ZHANG, Yu CAI, Abhiram PRABAHKAR
  • Publication number: 20240274519
    Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.
    Type: Application
    Filed: April 23, 2024
    Publication date: August 15, 2024
    Inventors: Yi-Min FU, Chi-Ching HO, Cheng-Yu KANG, Yu-Po WANG
  • Patent number: 12062687
    Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: August 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hong-Yang Chen, Tian Sheng Lin, Yi-Cheng Chiu, Hung-Chou Lin, Yi-Min Chen, Kuo-Ming Wu, Chiu-Hua Chung
  • Publication number: 20240264389
    Abstract: An electronic package and the manufacturing method thereof are provided, in which a photonic element and an electronic element are embedded in an encapsulation layer, and the photonic element has an external contact area exposed from the encapsulation layer, such that signals of the electronic element can be directly transmitted to an optical fiber via the external contact area of the photonic element to achieve the purpose of photoelectric integration.
    Type: Application
    Filed: May 2, 2023
    Publication date: August 8, 2024
    Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Che-Yu LEE, Po-Yuan SU
  • Patent number: 12051641
    Abstract: Provided is an electronic package providing a circuit structure having auxiliary circuit layers. Further, an electronic component is disposed on the circuit structure and electrically connected to the auxiliary circuit layers. In addition, an encapsulant covers the electronic component, and the circuit structure is disposed on the package substrate having a plurality of main circuit layers, such that the main circuit layers are electrically connected to the auxiliary circuit layers. As such, a number of layers of the auxiliary circuit layers is used to replace a layer number configuration of the main circuit layers.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: July 30, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min Fu, Chi-Ching Ho, Cheng-Yu Kang, Yu-Po Wang
  • Patent number: 12029282
    Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: July 9, 2024
    Assignee: NIKE, Inc.
    Inventors: Chun-Chieh Chen, Yi-Min Chen, Chia-Hung Lin, Hsien-Kuang Wu, Hung-Yu Wu
  • Publication number: 20240194744
    Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.
    Type: Application
    Filed: February 28, 2024
    Publication date: June 13, 2024
    Inventors: Yi-Cheng CHIU, Tian Sheng LIN, Hung-Chou LIN, Yi-Min CHEN, Chiu-Hua CHUNG
  • Publication number: 20240192262
    Abstract: A method includes providing a detector disposed above a semiconductor structure; identifying a portion of the semiconductor structure at a temperature substantially greater than a predetermined threshold by the detector, rotating the stage; and deriving a position of the portion of the semiconductor structure based upon the rotation of the stage.
    Type: Application
    Filed: February 21, 2024
    Publication date: June 13, 2024
    Inventors: YI MIN LIU, CHIEN-YI CHEN, YIAN-LIANG KUO
  • Publication number: 20240186415
    Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.
    Type: Application
    Filed: February 13, 2024
    Publication date: June 6, 2024
    Inventors: Chih-Yu Ma, Shahaji B. More, Yi-Min Huang, Shih-Chieh Chang
  • Patent number: 11996865
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Grant
    Filed: March 16, 2023
    Date of Patent: May 28, 2024
    Assignee: SK hynix Inc.
    Inventors: Kyoung Lae Cho, Soo Jin Kim, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
  • Publication number: 20240153884
    Abstract: An electronic package is provided, in which a first electronic element and a second electronic element stacked on each other are embedded in a cladding layer, a circuit structure electrically connected to the second electronic element is formed on the cladding layer, and a passive element and a package module are disposed on the circuit structure, so as to shorten the transmission distance of electrical signals between the package module and the second electronic element.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 9, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min FU, Hung-Kai WANG, Chi-Ching HO, Yih-Jenn JIANG, Yu-Po WANG