Patents by Inventor Yi MIN

Yi MIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12242313
    Abstract: A system determines a current state of an information handling system, and receives a sensor output signal. The system determines whether a status change of the sensor output signal relates to an expected state based on the current state and a previous state of the information handling system, and determines whether the sensor output signal is triggered by an external magnet. If the status change of the sensor output signal relates to the expected state and the sensor output signal is not triggered by the external magnet, then the system transitions the information handling system from the current state to the expected state.
    Type: Grant
    Filed: September 28, 2023
    Date of Patent: March 4, 2025
    Assignee: Dell Products L.P.
    Inventors: Chen Hsin Chang, Wan Shih Chien, Yi Min Lin
  • Publication number: 20250070517
    Abstract: A contact assembly for an electrical connector, includes: a row of contacts having plural contacting portions; an insulator secured to the contacting portions; an upper ground plate and a lower ground plate surrounding the row of contacts, at least one of the upper and lower ground plates integrally having plural ground contacting portions aligned with the contacting portions of the row of contacts; and plural separate conductive rivets electrically connecting the upper and lower ground plates.
    Type: Application
    Filed: August 19, 2024
    Publication date: February 27, 2025
    Inventors: PATRICK R. CASHER, TERRANCE F. LITTLE, CHUN-HSIUNG HSU, YI-MIN HSU, MING ZHOU
  • Publication number: 20250069138
    Abstract: The present invention proposes a method for constructing investment portfolios, which includes calculating the logarithmic return and the momentum factor through a processor based on historical stock prices, storing the logarithmic return and the momentum factor, the processor calculates the information coefficient (IC) values based on the logarithmic return and momentum factor, and stores the IC values as an investment target screening indicators, utilizes the processor to exanimate the momentum IC value in the time interval, deletes the stocks whose stock price is too small, ranks and stores the stocks according to the strength of the momentum, and utilizes the processor to determine the stock list in the portfolio based on the ranking by the equal weighting method, and then stores the portfolio.
    Type: Application
    Filed: September 22, 2023
    Publication date: February 27, 2025
    Inventors: Yi-Min Lan, Hung-Wen Cheng
  • Patent number: 12237458
    Abstract: A micro light emitting device display apparatus including a substrate, a plurality of micro light emitting devices, an isolation layer, and at least one first air gap is provided. The substrate has a plurality of connection pads. The micro light emitting devices are discretely disposed on the substrate. The isolation layer is disposed between the substrate and each of the micro light emitting devices. The at least one first air gap is disposed between the substrate and a surface of the isolation layer facing the substrate.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: February 25, 2025
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Chih-Ling Wu, Yen-Yeh Chen, Yi-Min Su, Yi-Chun Shih
  • Patent number: 12233515
    Abstract: A power tool includes a housing (10), a power device (20), a bearing set (30), a torque post (40) and a torque sensor (50). The housing (10) includes a main body (11) and a handle (12) perpendicularly connected to one side of the main body (11). The power device (20) is disposed in the main body (11) and includes a power body (21) and a bushing (22) adapted to sheathe the power body (21). The bearing set (30) is arranged between the bushing (22) and the housing (10). The power body (21) may rotate relative to the housing (10). The torque post (40) is disposed in the handle (12) and abuts against the bushing (22). The torque post (40) is arranged perpendicularly to the power body (21). The torque sensor (50) is disposed on the torque post (40).
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: February 25, 2025
    Assignee: MATATAKITOYO TOOL CO., LTD.
    Inventor: Yi-Min Wu
  • Publication number: 20250062856
    Abstract: The present disclosure provides a system for signal optimization adjustment based on different heat source information. The system includes a plurality of heat source measurers, a first system chip, a second system chip, an electrical interconnection, and a bit error risk evaluator. The first system chip includes a signal transmitter, and the second system chip includes a signal receiver. The second system chip provides an electrical characteristic state of the signal receiver, and a signal adjustment information of the signal transmitter and/or the signal receiver. The bit error risk evaluator performs a signal optimization adjustment for an electrical characteristic of the signal receiver according to the electrical characteristic state. The present disclosure further provides a method for signal optimization adjustment.
    Type: Application
    Filed: June 6, 2024
    Publication date: February 20, 2025
    Inventors: Wanfen TENG, Yi-Min YU, Jason YEH, Chao-Lung WEI, Fan-Cheng HUANG, Yi-Wen SU, Ting-Chu YEH, Mei-Yi HUANG
  • Patent number: 12229697
    Abstract: An example operation may include one or more of generating, by a blockchain node, an asset containment world-state by execution of a linear-time ingestion algorithm, detecting, by the blockchain node, an asset aggregation or disaggregation event, updating, by the blockchain node, the world-state based on the asset aggregation or disaggregation event, and computing supply-chain metrics based on the updated world-state.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: February 18, 2025
    Assignee: International Business Machines Corporation
    Inventors: Ashish Jagmohan, Yi-Min Chee, Julie MacNaught, Abhilash Narendra, Krishna Chaitanya Ratakonda, Ryan Enderby
  • Publication number: 20250056684
    Abstract: A heating device includes a resonant circuit, a detection unit and a control unit. The resonant circuit includes an inverter circuit and a resonant tank. The inverter circuit provides a resonant tank current and a resonant tank voltage. The resonant tank includes a heating coil, a resonant tank capacitor, a resonant tank equivalent inductor and a resonant tank equivalent resistor. The detection unit calculates an inductance of the resonant tank equivalent inductor according to a capacitance of the resonant tank capacitor, a resonant period and a first expression. The detection unit calculates a resistance of the resonant tank equivalent resistor according to the inductance of the resonant tank equivalent inductor, a time change value, a reference voltage value, a negative peak voltage value and a second expression.
    Type: Application
    Filed: December 27, 2023
    Publication date: February 13, 2025
    Inventors: Ming-Shi Huang, Zheng-Feng Li, Jhih-Cheng Hu, Yi-Min Chen, Chun-Wei Lin
  • Publication number: 20250038113
    Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.
    Type: Application
    Filed: October 16, 2024
    Publication date: January 30, 2025
    Inventors: Chao-Chiang PU, Chi-Ching HO, Yi-Min FU, Yu-Po WANG, Shuai-Lin LIU
  • Patent number: 12199047
    Abstract: An electronic package is provided in which an electronic module and a heat dissipation structure combined with the electronic module are disposed on a carrier structure, and at least one adjustment structure is coupled with the heat dissipation structure and located around the electronic module. Therefore, the adjustment structure disperses thermal stress to avoid warpage of the electronic module.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: January 14, 2025
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Po-Yuan Su
  • Publication number: 20250010432
    Abstract: A ratchet wrench includes a head, a toothed wheel, a pawl and a switch. The head includes two bores in communication with a pothole in communication with a chamber via a channel. The channel includes a broad section between two tapered sections. The toothed wheel is rotatable in the chamber. The switch is pivotable in the pothole and includes a tunnel with a first end in communication with the broad section of the channel and a second end in communication with the pothole. A spring is compressed between a detent and a ball. The detent includes an end connected to the pawl and another end movable in the tunnel. The ball includes a portion in the tunnel and another portion insertable in a selected one of the bores when the detent moves the pawl into a corresponding one of the tapered sections of the channel.
    Type: Application
    Filed: July 6, 2023
    Publication date: January 9, 2025
    Inventor: Yi-Min Li
  • Patent number: 12176291
    Abstract: An electronic package is provided in which a chip packaging module, an electronic element having a plurality of contacts, and an electronic connector are disposed on a routing structure of a carrier component, so as to communicatively connect with the chip packaging module via the electronic element and the electronic connector, thereby increasing a signal transmission speed.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: December 24, 2024
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chao-Chiang Pu, Chi-Ching Ho, Yi-Min Fu, Yu-Po Wang, Shuai-Lin Liu
  • Publication number: 20240421026
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure, a heat conduction layer is formed on the electronic element, and a heat dissipation member having a recess portion is disposed on the heat conduction layer to cover the electronic element. Therefore, the arrangement of the recess portion can buffer the flow of the heat conduction layer to facilitate the formation of an intermetallic structure with sufficient thickness between the heat dissipation member and the electronic element, and the heat dissipation effect of the electronic element can meet expectations.
    Type: Application
    Filed: August 11, 2023
    Publication date: December 19, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chiu-Ling CHEN, Shuai-Lin LIU, Pin-Jing SU, Yi-Min FU, Lung-Yuan WANG
  • Publication number: 20240413749
    Abstract: A multilevel buck converter includes a plurality of switches, an inductor, a flying capacitor, and a control circuit. The plurality of switches are coupled between an input terminal and a ground. The input terminal has an input voltage. The inductor is coupled between the plurality of switches and an output terminal for generating an inductor-current signal. The flying capacitor is coupled to the plurality of switches for generating a flying capacitor voltage. The control circuit is coupled to the output terminal and the plurality of switches for generating a plurality of switching signals according a feedback voltage and the inductor-current signal. The control circuit operates in a valley current mode with dual slope compensation.
    Type: Application
    Filed: August 31, 2023
    Publication date: December 12, 2024
    Inventors: Kuo-Chi Liu, Ta-Yung Yang, Yi-Min Shiu
  • Patent number: 12161199
    Abstract: Buffing of a footwear component allows for an alteration of the component surface to achieve an intended surface for aesthetics and/or manufacturing purposes. The buffing is performed in a system having a vision module, a sidewall buffing module, an up surface buffing module, and a down surface buffing module. Each of the buffing modules are adapted for the unique shape and sizes of a footwear component to effectively and automatically buff the footwear component.
    Type: Grant
    Filed: December 7, 2022
    Date of Patent: December 10, 2024
    Assignee: NIKE, Inc.
    Inventors: Chun-Chieh Chen, Yi-Min Chen, Chia-Hung Lin, Hsien-Kuang Wu, Hung-Yu Wu
  • Publication number: 20240395937
    Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Yi-Min Huang, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20240379590
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure with a circuit layer, a first encapsulating layer and a second encapsulating layer are formed on the carrier structure to cover the electronic element, a first antenna layer is formed on the first encapsulating layer, and a second antenna layer communicatively connected to the first antenna layer is formed on the second encapsulating layer. Therefore, the thickness of the first encapsulating layer is used to control the resonance distance of the antenna frequency so as to generate better resonance effect, and the distance between the first antenna layer and the second antenna layer is controlled by the thickness of the second encapsulating layer to increase the bandwidth of the antenna.
    Type: Application
    Filed: August 11, 2023
    Publication date: November 14, 2024
    Inventors: Chia-Chu LAI, Yi-Min FU, Chien-Sheng CHEN
  • Patent number: 12142681
    Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Min Huang, Shih-Chieh Chang, Cheng-Han Lee
  • Publication number: 20240371721
    Abstract: An electronic package and a manufacturing method thereof are provided, in which a heat sink with an opening is disposed on an electronic component of a carrier structure, a heat dissipation material is formed in the opening, and a heat dissipation lid is disposed on the opening to cover the heat dissipation material, such that the problem of insufficient heat dissipation due to the loss of the heat dissipation material can be prevented from occurring to the electronic component.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 7, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Min FU, Chi-Ching HO, Chao-Chiang PU, Yu-Po WANG
  • Publication number: 20240363680
    Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.
    Type: Application
    Filed: July 11, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hong-Yang CHEN, Tian Sheng LIN, Yi-Cheng CHIU, Hung-Chou LIN, Yi-Min CHEN, Kuo-Ming WU, Chiu-Hua CHUNG