Abstract: An illumination device includes an OLED panel, an electrode structure, and a control module. The OLED panel includes a light-emitting layer configured to emit a light beam. The electrode structure is overlaid on the OLED panel. The electrode structure includes a first touch electrode including at least two conductive portions, and the conductive portions of the first touch electrode are electrically connected to the other conductive portions. The control module is electrically connected to the OLED panel and the first touch electrode. The light-emitting layer further includes a light-emitting material, and a width of the light-emitting material is greater than half of a width of the first touch electrode.

Abstract: An electric field-induced carrier generation layer including a p-type material and an n-type material is provided. The p-type material and the n-type material are alternately distributed in at least one direction different from a thickness direction of the electric field-induced carrier generation layer. An organic electronic device is also provided.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract: An electric field-induced carrier generation layer including a p-type material and an n-type material is provided. The p-type material and the n-type material are alternately distributed in at least one direction different from a thickness direction of the electric field-induced carrier generation layer. An organic electronic device is also provided.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a first recess extending from the first surface towards the second surface; a second recess extending from a bottom of the first recess towards the second surface, wherein a sidewall and the bottom of the first recess and a second sidewall and a second bottom of the second recess together form an exterior side surface of the semiconductor substrate; a wire layer disposed over the first surface and extending into the first recess and/or the second recess; an insulating layer positioned between the wire layer and the semiconductor substrate; and a metal light shielding layer disposed over the first surface and having at least one hole, wherein a shape of the at least one hole is a quadrangle.

Abstract: A method of manufacturing chip package includes providing a semiconductor substrate having at least a photo diode and an interconnection layer. The interconnection layer is disposed on an upper surface of the semiconductor substrate and above the photo diode and electrically connected to the photo diode. At least a redistribution circuit is formed on the interconnection layer. The redistribution circuit is electrically connected to the interconnection layer. A packaging layer is formed on the redistribution circuit. Subsequently, a carrier substrate is attached to the packaging layer. A colour filter is formed on a lower surface of the semiconductor substrate. A micro-lens module is formed under the colour filter. The carrier substrate is removed.

Abstract: An organic light emitting device (OLED) is provided, may comprise a first organic electroluminescent cell, a second organic electroluminescent cell, a charge generation layer, disposed between the first and second organic electroluminescent cells, a first electrode and a second electrode formed at the first and second organic electroluminescent cells. The first organic electroluminescent cell comprises a fluorescent light emitting layer having a fluorescent emitting element and a phosphorescent light emitting layer having a phosphorescent emitting element. The second organic electroluminescent cell comprises at least one light emitting layer.

Abstract: A chip package is provided. The chip package includes a semiconductor chip, an isolation layer, a redistributing metal layer, and at least a bonding pad. The semiconductor chip includes at least one conducting disposed on a surface of the semiconductor chip. The isolation layer is disposed on the surface of the semiconductor chip, wherein the isolation layer has at least one first opening to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has at least a redistributing metal line corresponding to the conducting pad, the redistributing metal line is connected to the first conducting pad through the first opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the conducting pad to the bonding pad.

Abstract: An illumination device including a light-emitting panel, a touch panel, and a control module is provided. The light-emitting panel includes a light-emitting layer configured to emit a light beam. The touch panel is overlaid on the light-emitting panel, and includes a first touch electrode. The control module is electrically connected to the light-emitting panel and the touch panel. The light-emitting layer further includes a light-emitting material, and the width of the light-emitting material is greater than half of the width of the first touch electrode.

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A first isolation layer is formed on a first surface of a wafer substrate. A conductive pad is formed on the first isolation layer. A hollow region through the first surface and a second surface of the wafer substrate is formed, such that the first isolation layer is exposed through the hollow region. A laser etching treatment is performed on the first isolation layer that is exposed through the hollow region, such that a first opening is formed in the first isolation layer, and a concave portion exposed through the first opening is formed in the conductive pad.

Abstract: An illumination device includes an OLED panel, an electrode structure, and a control module. The OLED panel includes a light-emitting layer configured to emit a light beam. The electrode structure is overlaid on the OLED panel. The electrode structure includes a first touch electrode including at least two conductive portions, and the conductive portions of the first touch electrode are electrically connected to the other conductive portions. The control module is electrically connected to the OLED panel and the first touch electrode. The light-emitting layer further includes a light-emitting material, and a width of the light-emitting material is greater than half of a width of the first touch electrode.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.

Abstract: An embodiment of this invention provides a separation apparatus for separating a stacked article, such as a semiconductor chip package with sensing functions, comprising a substrate and a cap layer formed on the substrate. The separation apparatus comprises a vacuum nozzle head including a suction pad having a top surface and a bottom surface, a through hole penetrating the top surface and the bottom surface of the suction pad, and a hollow vacuum pipe connecting the through hole to a vacuum pump; a stage positing under the vacuum nozzle head and substantially aligning with the suction pad; a control means coupling to the vacuum nozzle head to lift upward or lower down the vacuum nozzle head; and a first cutter comprising a first cutting body and a first knife connecting to the first cutting body.

Abstract: A method for forming a chip package is provided. The method includes providing a substrate and a capping layer, wherein the substrate has a sensing device therein adjacent to a surface of the substrate. The capping layer is attached to the surface of the substrate by an adhesive layer, wherein the adhesive layer covers the sensing device. A dicing process is performed on the substrate, the adhesive layer, and the capping layer along a direction to form individual chip packages.

Abstract: A method for forming a chip package is provided. The method includes providing a first substrate and a second substrate. The first substrate is attached onto the second substrate by an adhesive layer. A first opening is formed to penetrate the first substrate and the adhesive layer and separate the first substrate and the adhesive layer into portions. A chip package formed by the method is also provided.

Abstract: An embodiment of the present invention relates to a chip package and fabrication method thereof, which includes a semiconductor substrate containing a chip area and a peripheral pad area surrounding the chip area, wherein a conductive pad and a through hole exposing the conductive pad are formed in the peripheral pad area; a protection layer covering a bottom surface of the semiconductor substrate and the through hole; a packaging layer formed on an upper surface of the semiconductor substrate; and a spacing layer formed between the packaging layer and the semiconductor substrate, wherein the chip packaging has a main side surface constituted of side surfaces of the semiconductor substrate, the protecting layer, the packaging layer and the spacing layer, and wherein the main side surface has at least one recess portion.

Abstract: An illumination device including a light-emitting panel, a touch panel, and a control module is provided. The light-emitting panel includes a light-emitting layer configured to emit a light beam. The touch panel is overlaid on the light-emitting panel, and includes a first ouch electrode. The control module is electrically connected to the light-emitting panel and the touch panel. The light-emitting layer further includes a light-emitting material, and the width of the light-emitting material is greater than half of the width of the first touch electrode.

Abstract: A wafer packaging method includes the following steps. A wafer having a plurality of integrated circuit units is provided. A first surface of the wafer opposite to the integrated circuit units is ground. A release layer is formed on a second surface of a light transmissive carrier. An ultraviolet temporary bonding layer is formed on the second surface of the light transmissive carrier or a third surface of the wafer. The ultraviolet temporary bonding layer is used to adhere the second surface of the light transmissive carrier to the third surface of the wafer. The first surface of the wafer is adhered to an ultraviolet tape. A fourth surface of the light transmissive carrier is exposed to ultraviolet to eliminate adhesion force of the ultraviolet temporary bonding layer. The light transmissive carrier and the release layer are removed.

Abstract: Provided is a conductive structure and a device with the conductive structure as an electrode. The conductive structure includes a reduced metal layer and an overlapping structure formed by nano metal wires. The overlapping structure has at least one connecting portion, and the reduced metal layer covers the nano metal wires at the connecting portions.

Abstract: A chip package is provided. The chip package includes a semiconductor chip, an isolation layer, a redistributing metal layer, and at least a bonding pad. The semiconductor chip includes at least one conducting disposed on a surface of the semiconductor chip. The isolation layer is disposed on the surface of the semiconductor chip, wherein the isolation layer has at least one first opening to expose the first conducting pad. The redistributing metal layer is disposed on the isolation layer and has at least a redistributing metal line corresponding to the conducting pad, the redistributing metal line is connected to the first conducting pad through the first opening. The bonding pad is disposed on the isolation layer and one side of the semiconductor chip, wherein the redistributing metal line extends to the bonding pad to electrically connect the conducting pad to the bonding pad.