Abstract: An apparatus for treating a nail plate or a skin using plasma is provided. The apparatus comprises a plasma generation assembly, a power supply, and a grounding electrode. The plasma generation assembly comprises a positive electrode module and a curved surface dielectric layer. The positive electrode module includes a discharging face. The curved surface dielectric layer includes a first surface and a second surface opposite to the first surface, wherein the first surface is adjacent to the discharging face, and clearances outside the second surface or holes from the first surface to the second surface are used for high frequency plasma generation. The clearances form a closed room. The power supply powers the plasma generation assembly so as to generate a current from the discharging face to the grounding electrode.

Abstract: A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Abstract: A memory array includes at least one strap region, at least two sub-arrays, a plurality of staggered, dummy magnetic storage elements, and a plurality of bit line structures. The strap region includes a plurality of source line straps and a plurality of word line straps. The two sub-arrays include a plurality of staggered, active magnetic storage elements. The two sub-arrays are separated by the strap region. The staggered, dummy magnetic storage elements are disposed within the strap region. The bit line structures are disposed in the two sub-arrays, and each of the bit line structures is disposed above and directly connected with at least one of the staggered, active magnetic storage elements.

Abstract: A multidirectional optical element includes a substrate and a metalens. The metalens is disposed on the substrate and has a metastructure, wherein the metastructure includes a pattern of a diffractive optical element.

Abstract: The present invention provides novel serine recombinases, recombinase based systems and compositions, and methods for genomic targeting and modification. In some aspects, the large serine recombinases, and systems thereof are used to treat human diseases.

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a cap layer on sidewalls of the first MTJ and the second MTJ, a dielectric layer around and directly contacting the cap layer, a first metal interconnection on the first MTJ, the second MTJ, and the dielectric layer, and an inter-metal dielectric (IMD) layer around the dielectric layer and the first metal interconnection.

Abstract: Some implementations described herein provide a deposition tool and methods of operation. The deposition tool may be used in the fabrication of integrated circuit devices to deposit materials and/or layers on a semiconductor substrate. The deposition tool may include a chamber (e.g., a processing chamber) that is coated with a dielectric coating on sidewalls of the chamber. The dielectric coating on the sidewalls of the chamber within the deposition tool increases a likelihood of a negative charge accumulating near the sidewalls of the chamber. The increased likelihood of negative charge accumulation near the sidewalls of the chamber may improve a uniformity of an electromagnetic field within the deposition tool (e.g., during a deposition operation) relative to another deposition too not including such a dielectric coating. The improved uniformity of the electromagnetic field may enable an improved uniformity of a material being deposited by the deposition tool to be achieved.

Abstract: A depth camera capable of measuring the oblique velocity of an object is provided, wherein a depth camera capable of measuring the lateral velocity of an object includes a depth camera body, a first configuration file, and a lateral velocity calculation system. The lateral velocity calculation system includes: first image-processing software for recording a first depth distance at which images are taken of an object and for calculating the number of pixels corresponding to a lateral movement of the object and the duration of the lateral movement; and lateral velocity calculation software for calculating the lateral velocity of the object. The depth camera capable of measuring the oblique velocity of an object allows the lateral/longitudinal/oblique velocity of an object to be measured in real time using image-related techniques.

Abstract: A memory structure includes a bottom via, a memory cell and a top via. The memory cell is disposed on the bottom via and includes a bottom electrode, a top electrode and a first storage element layer and a second storage element layer sandwiched between the bottom electrode and the top electrode. The first storage element layer is in contact with the bottom electrode, and a crystallization temperature of the first storage element layer is higher than a crystallization temperature of the second storage element layer. The top via is disposed on the memory cell and electrically connected to the top electrode.

Abstract: A couple-in lens assembly includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens, a sixth lens, a seventh lens, an eighth lens and a ninth lens. The second lens is located above the first lens. The third lens is attached above the second lens. The fourth lens is located above the third lens. The fifth lens is located above the fourth lens. The sixth lens is attached above the fifth lens. The seventh lens is located above the sixth lens. The eighth lens is located above the seventh lens. The ninth lens is attached above the eighth lens.

Abstract: A recommendation system leverages multi-target search to provide item listing recommendations and/or query suggestions. For a given input image with multiple objects, multi-target search uses object detection to detect each object, and stores complementary object data associating each object from the image. Additionally, a search of an item listing datastore is performed using each object from the image as a search query. Based on item listings returned as search results, complementary item listings data associating item listings is stored. In some configurations, the complementary item listings data is also used to train a machine learning model to predict complementary item listings for a given item listing. When an input item listing is received, item listing recommendations and/or query suggestions are determined for the input item listing using the complementary object data, the complementary item listing data, and/or the machine learning model.

Abstract: In some embodiments, the present disclosure relates to a microelectromechanical system (MEMS) comb actuator including a comb structure. The comb structure includes a support layer having a first material and a plurality of protrusions extending away from a first surface of the support layer in a first direction. The plurality of protrusions are also made of the first material. The plurality of protrusions are separated along a second direction parallel to the first surface of the support layer. The MEMS comb actuator may further include a dielectric liner structure that continuously and completely covers the first surface of the support layer and outer surfaces of the plurality of protrusions. The dielectric liner structure includes a connective portion that continuously connects topmost surfaces of at least two of the plurality of protrusions.

Abstract: A processing apparatus comprises a transmit path of a first communication system, a transmit path of a satellite communication system, a receive path of the satellite communication system, and a first calibration path. The first communication system and the satellite communication system share the receive path of the satellite communication system. A first end of the first calibration path is connected to the transmit path of the first communication system, or a first end of the first calibration path is connected to the transmit path of the satellite communication system. A second end of the first calibration path is connected to the receive path of the satellite communication system. When the first calibration path is connected to the satellite communication system, the first calibration path may be used to calibrate the satellite communication system.

Abstract: A transmit power adjustment method includes obtaining a first signal sequence, where the first signal sequence includes a valid signal sequence; controlling a first module and a second module to adjust transmit power of the first signal sequence; and sending the first signal sequence. The first module is configured to coarsely adjust the transmit power of the first signal sequence. The second module is configured to finely adjust the transmit power of the first signal sequence. After obtaining the first signal sequence, a transmitter may steadily adjust the transmit power of the first signal sequence by using the first module and the second module, and correspondingly send the valid signal sequence in the first signal sequence when the transmit power reaches the first transmit power threshold and/or the second transmit power threshold.

Abstract: A chip includes a satellite communication system radio frequency (RF) path, a first satellite positioning system RF path, and a first phase-locked loop (PLL). The satellite communication system RF path and the first satellite positioning system RF path share the first PLL.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

Abstract: A method of manufacturing a hybrid random access memory in a system-on-chip, including steps of providing a semiconductor substrate with a magnetoresistive random access memory (MRAM) region and a resistive random-access memory (ReRAM) region, forming multiple ReRAM cells in the ReRAM region on the semiconductor substrate, forming a first dielectric layer on the semiconductor substrate, wherein the ReRAM cells are in the first dielectric layer, forming multiple MRAM cells in the MRAM region on the first dielectric layer, and forming a second dielectric layer on the first dielectric layer, wherein the MRAM cells are in the second dielectric layer.

Abstract: In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes introducing a first processing gas of an atomic layer deposition (ALD) process on the semiconductor substrate in a chamber; introducing a second processing gas of the ALD process on the semiconductor substrate in the chamber; creating an exhaust flow from the chamber; monitoring a concentration of the first processing gas of the ALD process in the exhaust flow; in response to the monitored concentration of the first processing gas of the ALD process in the exhaust flow, introducing a cleaning gas into the chamber.

Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.

Abstract: A manufacturing method of a semiconductor device includes at least the following steps. A sacrificial substrate is provided. An etch stop layer is formed on the sacrificial substrate. A portion of the etch stop layer is oxidized to form an oxide layer between the sacrificial substrate and the remaining etch stop layer. A capping layer is formed on the remaining etch stop layer. A device layer is formed on the capping layer. A first etching process is performed to remove the sacrificial substrate. A second etching process is performed to remove the oxide layer. A third etching process is performed to remove the remaining etch stop layer. A power rail is formed on the capping layer opposite to the device layer.