Patents by Inventor Yi Yu

Yi Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240427815
    Abstract: Provided are a method for multimedia recommendation and an apparatus thereof. The method for multimedia recommendation includes: obtaining first user data of a user wearing a wearable device that is collected by the wearable device; obtaining second user data of the user, where the second user data includes at least one of attribute data of the user or multimedia preference data of the user; obtaining scenario data corresponding to a current multimedia usage scenario; determining a target multimedia item from a plurality of candidate multimedia items based on the first user data, the second user data and the scenario data; and recommending the target multimedia item to the user.
    Type: Application
    Filed: September 10, 2024
    Publication date: December 26, 2024
    Inventors: Cong Zhang, Yi Yu, Zi Meng, Guokang Zhu
  • Publication number: 20240428745
    Abstract: A processing system for simultaneously presenting brightness performance of different areas on a single display screen includes: a detection processor and a control processor. The detection processor performs a multi-point photometry of a pre-imaging area to find out the difference in ambient light intensity distribution among the points on the display screen after a display device is installed, where the pre-imaging area refers to an area of a display device set up or projected for viewing. The control processor connected to the detection processor for correspondingly cutting a screen range of the display device into multiple modulation areas based on the ambient light intensity difference of the pre-imaging area. In this way, the display screen can be adjusted to adapt to various environments with differences in brightness or position.
    Type: Application
    Filed: June 12, 2024
    Publication date: December 26, 2024
    Inventors: YI-YU TSAI, SHAO-WEI CHIU, YIN-CHENG HUANG
  • Publication number: 20240421235
    Abstract: A semiconductor device and a semiconductor device manufacturing method. The semiconductor device includes: a substrate; an epitaxial layer, located on one side of the substrate, where a doped region is formed on a surface that is of the epitaxial layer and that is away from the substrate, and the epitaxial layer includes an active region and a termination region that surrounds the active region; a passivation layer, covering the termination region and on which a window corresponding to the active region is formed; and a metal layer, covering the window and an inner edge that is of the passivation layer and that forms the window, and forming a schottky contact with the active region in the window.
    Type: Application
    Filed: August 23, 2024
    Publication date: December 19, 2024
    Applicant: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Yi YU, Chia Fu LIU, Yuru WANG, Bo GAO, Longgu TANG, Xin WANG, Dongguang ZHAO, Shijin LUO
  • Publication number: 20240423023
    Abstract: A display panel in the present application includes: a base plate; a plurality of first electrodes disposed on a side of the base plate, first openings are formed between adjacent ones of the first electrodes; an insulation layer disposed on a side of the first electrodes away from the base plate, at least a part of the insulation layer is located within the first openings, the insulation layer includes second openings that run through the insulation layer, and an orthographic projection of the second opening on the base plate overlaps at least partially with an orthographic projection of the first electrode on the base plate; and at least one isolation structure disposed on a side of the insulation layer away from the base plate, an orthographic projection of the first opening on the base plate is located within an orthographic projection of the isolation structure on the base plate.
    Type: Application
    Filed: May 3, 2024
    Publication date: December 19, 2024
    Applicant: Hefei Visionox Technology Co., Ltd.
    Inventors: Liusong NI, Yiming XIAO, Yuan YAO, Yi-Yu LAI, Xuejing ZHU
  • Publication number: 20240421187
    Abstract: A semiconductor device (having a VFET architecture) includes: first and second active regions (ARs); first and second metal-to-gate (MG) contacts proximal to channel regions of the first and second ARs; metal-to-source/drain (MD) contacts and buried MD (BMD) contacts correspondingly coupled to first and second S/D regions correspondingly of the first and second ARs; and a metal-to-gate (MP) contact at a same level as the MG contacts, and extending between and coupling together the first and second MG contacts; and relative to a first direction, the first and second ARs being substantially aligned; and at least a portion of the MP contact extending substantially beyond each of the first and second ARs relative to a perpendicular second direction.
    Type: Application
    Filed: June 16, 2023
    Publication date: December 19, 2024
    Inventors: Yi Yu CHEN, Chi-Yu LU, Chih-Liang CHEN
  • Publication number: 20240398901
    Abstract: The present application provides a process for manufacturing an orally disintegrating tablet (ODT) comprising a cytokine as an active pharmaceutical ingredient comprising: acidifying an excipient, conducting a first granulation step of the acidified excipient to obtain acidic powders, and conducting a second granulation step by mixing the acidic powders and the cytokine to obtain granules containing the cytokine. The present application also provides an ODT manufactured by the process.
    Type: Application
    Filed: June 4, 2024
    Publication date: December 5, 2024
    Applicant: AINOS INC. TAIWAN BRANCH (USA)
    Inventors: Tsung-Fu YU, Yi-Yu TIEN, Chun-Hsien TSAI, Ting-Chuan LEE, Chun-Jung TSAI
  • Publication number: 20240384089
    Abstract: A contact lens including at least one silicone monomer is provided, wherein the surface of the contact lens includes polyacrylic acid and/or sodium polyacrylate, and the molecular weight of the polyacrylic acid and/or the sodium polyacrylate is greater than 100 kDa. The present invention further provides a silicone hydrogel contact lens. The contact lens and the silicone hydrogel contact lens provided by the present invention have the advantages of good hydrophilicity and being suitable for consumers' long-time wearing.
    Type: Application
    Filed: May 13, 2024
    Publication date: November 21, 2024
    Inventors: WEI-HANG HSU, CHU-YI YU, YAO-TSUNG CHENG
  • Patent number: 12148706
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: November 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Chung-Yi Yu, Kuei-Ming Chen
  • Publication number: 20240381793
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a bottom electrode over a substrate. A top electrode overlies the bottom electrode. A capping structure is disposed between the top electrode and the bottom electrode. The capping structure comprises a diffusion barrier layer vertically stacked with a metal layer. A switching structure is disposed between the bottom electrode and the capping structure. The switching structure comprises a dielectric layer on the bottom electrode and a first oxygen affinity layer on the dielectric layer. A first Gibbs free energy of the first oxygen affinity layer is less than a second Gibbs free energy of the dielectric layer. A first difference between the first Gibbs free energy and the second Gibbs free energy is less than ?100 kJ/mol.
    Type: Application
    Filed: January 29, 2024
    Publication date: November 14, 2024
    Inventors: Fa-Shen Jiang, Hai-Dang Trinh, Cheng-Yuan Tsai, Chung-Yi Yu
  • Publication number: 20240379724
    Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an epitaxial structure disposed on a semiconductor substrate. A photodetector is disposed at least partially in the epitaxial structure. A first capping layer is disposed on the semiconductor substrate and covers the epitaxial structure. A second capping layer is disposed vertically between the first capping layer and the epitaxial structure. The first capping layer extends laterally past outermost sidewalls of the epitaxial structure and the second capping layer.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 14, 2024
    Inventors: Po-Chun Liu, Chung-Yi Yu, Eugene Chen
  • Publication number: 20240379570
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Xin-Hua Huang, Chung-Yi Yu, Kuei-Ming Chen
  • Patent number: 12140794
    Abstract: A light source module includes a light guide plate including a light entrance surface and a light source adjacent to the light entrance surface. The light source includes a light emitting device to emit a blue light, a first wavelength conversion unit on the light emitting device and a second wavelength conversion unit on the light emitting unit. When the blue light is incident to the first wavelength conversion unit, the blue light is converted into a first light. The first light has a wavelength in a range from 480 nm to 650 nm. When the blue light is incident to the second wavelength conversion unit, the blue light is converted to a second light. The second light has a wavelength different from the wavelength of the first light. The blue light, the first light and the second light combine to produce a white light.
    Type: Grant
    Filed: November 1, 2023
    Date of Patent: November 12, 2024
    Assignee: E Ink Holdings Inc.
    Inventors: Yi-Yu Tsai, Ching-Huan Liao
  • Publication number: 20240350783
    Abstract: A dissolvable microneedle patch includes a microneedle portion and a patch portion. The microneedle portion has a base and a plurality of microneedles. The base has a first surface and a second surface opposite thereto. The microneedles are connected to the first surface. The patch portion is connected to the second surface. The microneedle portion is made from a mixture, and the mixture includes an excipient. The excipient includes sodium alginate and dextrin, and a weight ratio of the dextrin to the sodium alginate is 0.2 to 1. In addition, the present invention also provides a method to produce the dissolvable microneedle patch.
    Type: Application
    Filed: August 11, 2023
    Publication date: October 24, 2024
    Inventors: JEN SHUN LIN, Jyun-Yi Yu, YunPei Yang
  • Patent number: 12115700
    Abstract: A drying oven for 3D printing materials includes a base, an upper cover, a rotating shaft assembly and a drying assembly. The drying assembly includes a heating plate and a fan. An air outlet end of the fan faces upward, and the heating plate is arranged above the air outlet end of the fan. An accommodating cavity is provided at a middle of the base, and an air inlet communicating with outside is provided at a bottom of the accommodating cavity. The fan and the heating plate are arranged in the accommodating cavity. The rotating shaft assembly is arranged on a top surface of the base. An air outlet is arranged at an upper end of the upper cover, and the upper cover is configured to cover the base.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: October 15, 2024
    Assignee: Shenzhen EIBOS Chuanggou Tech Co., Ltd
    Inventors: Dezhen Chen, Yubo Shen, Yi Yu, Yueyi Yu
  • Publication number: 20240339422
    Abstract: Some implementations described herein provide techniques and apparatuses for forming a stacked die product including two or more integrated circuit dies. A bond interface between two integrated circuit dies that are included in the stacked die product includes a layered structure. As part of the layered structure, respective layers of a sealant material are directly on co-facing surfaces of the two integrated circuit dies. The layered structure further includes one or more bonding layers between the respective layers of the sealant material that are directly on the co-facing surfaces of the two integrated circuit dies. The layered structure may reduce lateral stresses throughout the bond interface to reduce a likelihood of warpage of the two integrated circuit dies.
    Type: Application
    Filed: April 10, 2023
    Publication date: October 10, 2024
    Inventors: Che Wei YANG, Kuo-Ming WU, Sheng-Chau CHEN, Cheng-Yuan TSAI, Hau-Yi HSIAO, Chung-Yi YU
  • Publication number: 20240330432
    Abstract: An apparatus, a method, and a system are presented in which the apparatus includes an interface control circuit that may be configured to receive a message including a cryptographic keyword and a policy value. The policy value may include one or more data bits indicative of one or more policies that define allowable usage of the cryptographic keyword. The apparatus also includes a security circuit that may be configured to extract the cryptographic keyword and the policy value from the message, and to apply at least one policy of the one or more policies to usage of the cryptographic keyword in response to a determination that an authentication of the message succeeded.
    Type: Application
    Filed: March 1, 2024
    Publication date: October 3, 2024
    Inventors: Timothy R. Paaske, Weihua Mao, Shu-Yi Yu
  • Publication number: 20240332026
    Abstract: A substrate grinding tool is configured to remove material from a semiconductor substrate in a grinding operation. In the grinding operation, the substrate grinding tool uses a combination of mechanical grinding and a chemical etchant to remove material from the semiconductor substrate. The chemical etchant may be heated to a high temperature, which may increase the etch rate of the chemical etchant. The use of the combination of mechanical grinding and the chemical etchant may increase the grinding rate of the substrate grinding tool for grinding semiconductor substrates, may reduce surface roughness for semiconductor substrates that are processed by the substrate grinding tool, and/or may reduce surface damage for semiconductor substrates that are processed by the substrate grinding tool, among other examples.
    Type: Application
    Filed: May 31, 2023
    Publication date: October 3, 2024
    Inventors: Chi-Fan CHEN, Chun-Kai LAN, Zhen Yu GUAN, Hsun-Chung KUANG, Cheng-Yuan TSAI, Chung-Yi YU
  • Publication number: 20240319483
    Abstract: A volume holographic optical element projection system includes a projection lens, a polarizing beam splitter, a liquid crystal on silicon panel, and a volume holographic optical element. The projection lens includes a light incident side, a light emitting side, and nine lenses. A f-number of the projection lens is in a range from 1 to 3. The f-number is a value derived from dividing the focal length by the entrance pupil diameter. The liquid crystal on silicon panel includes a protection glass. The polarizing beam splitter is located between the light incident side of the projection lens and the protection glass of the liquid crystal on silicon panel. The light emitting side of the projection lens faces the volume holographic optical element.
    Type: Application
    Filed: August 3, 2023
    Publication date: September 26, 2024
    Inventors: Wen-Hsin SUN, Wei-Chia SU, Jun-Yi YU, Ching-Cherng SUN
  • Publication number: 20240323131
    Abstract: Systems and methods for synchronizing motion connection communication to time-aware network for industrial systems. One system includes an electronic processor configured to determine a controller Qbv configuration for an industrial controller included in a TSN. The electronic processor is also configured to determine, based at least in part on the controller Qbv configuration, a first start of a Qbv slot for isochronous traffic for an industrial device included in the TSN. The electronic processor is also configured to adjust, based at least in part on the first start of the Qbv slot for isochronous traffic for the industrial device, network scheduling for the industrial device. The electronic processor is also configured to deploy the adjusted network scheduling to the industrial device.
    Type: Application
    Filed: March 20, 2023
    Publication date: September 26, 2024
    Inventors: Dayin XU, Chao CHEN, Yi YU, Mark R. COOPER, Jun LI
  • Publication number: 20240319431
    Abstract: A display device includes a reflective display panel, a light guide plate, a first resin layer, a second resin layer, and a first optical adhesive layer. The light guide plate has a top surface and a bottom surface. The first resin layer includes a light guide entrance and a leveled region. The first resin layer is located on the bottom surface. The second resin layer is located on the top surface and has a microstructure. The first optical adhesive layer is located between the reflective display panel and the light guide plate. The refractive index of the leveled region of the first resin layer and the refractive index of the first optical adhesive layer are the same.
    Type: Application
    Filed: March 19, 2024
    Publication date: September 26, 2024
    Inventor: Yi-Yu TSAI