Abstract: A computer-implemented method includes identifying a webpage comprising a set of user interface (UI) elements, analyzing the set of user UI elements to identify a set of interactable elements, classifying the elements of the set interactable elements as either focusable or not focusable, extracting features from source code corresponding to interactable elements of the set of interactable elements classified as focusable, and building an accessibility issue detection model using the extracted features from source code corresponding to focusable interactable elements as training data. The method may further include extracting features from source code corresponding to interactable elements classified as not focusable and updating the accessibility issue detection model using the extracted features from source code corresponding to interactable elements which are not focusable as training data.

Abstract: A computer-implemented method, according to one embodiment, includes using a trained semantic consistency model to determine a semantic consistency of contents of two screenshots. The trained semantic consistency model bases the semantic consistency on dimensions including: a linguistic comparison of the contents, an image comparison of the contents and a text location comparison of the contents. The method further includes outputting the determined semantic consistency for display on a user device. A computer program product, according to another embodiment, includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and/or executable by a computer to cause the computer to perform the foregoing method. A system, according to another embodiment, includes a processor, and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor.

Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.

Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.

Abstract: A composite frame includes a frame body including two support units, two lower connecting rods, two suspending units and an upper connecting rod that are removably connectable together so that the constructed frame body is structurally stable, while assembly and disassembly of the same are manually operable and convenient to allow for effective storage and cost reduction in terms of packaging and delivery.

Abstract: A composite frame includes a frame body including two support units, two lower connecting rods, two suspending units and an upper connecting rod that are removably connectable together so that the constructed frame body is structurally stable, while assembly and disassembly of the same are manually operable and convenient to allow for effective storage and cost reduction in terms of packaging and delivery.

Abstract: An exemplary embodiment provides a method for swing result deduction and posture correction. The method includes performing a coordinate transformation between a sensor frame and an earth frame, deducting the swing result according to at least one piece of sensor information and a swing result deduction analysis, and providing a posture correction advice according to at least one piece of sensor information and a posture correction analysis.

Abstract: A method includes forming a gate stack over a semiconductor substrate, wherein the gate stack includes a gate dielectric and a gate electrode over the gate dielectric. A portion of the semiconductor substrate adjacent to the gate stack is recessed to form a recess. A semiconductor region is epitaxially grown in the recess. The semiconductor region is implanted with a p-type impurity or an n-type impurity. A dry treatment is performed on the semiconductor region.

Abstract: A method includes forming a gate stack over a semiconductor substrate, wherein the gate stack includes a gate dielectric and a gate electrode over the gate dielectric. A portion of the semiconductor substrate adjacent to the gate stack is recessed to form a recess. A semiconductor region is epitaxially grown in the recess. The semiconductor region is implanted with a p-type impurity or an n-type impurity. A dry treatment is performed on the semiconductor region.

Abstract: A baby walker includes a protective seat unit, a base ring unit, and a plurality of wheel units. The protective seat unit includes a bottom ring, at least one protective ring stacked above the bottom ring, and a seat connected to the protective ring. The bottom ring and the protective ring are inflatable. The base ring unit is detachably disposed under the bottom ring. The base ring unit includes a plurality of bottom rods removably connected to each other, and a plurality of fasteners fastening the bottom rods together. Each of the wheel units is attached to a bottom end of the base ring unit and includes a caster.

Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.

Abstract: A method of fabricating a semiconductor device is illustrated. A modified profile opening is formed on a substrate. The modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate. The second width is greater than the first width. A metal gate electrode is formed by filling the modified profile opening with a conductive material. A semiconductor device is also described, the device having a metal gate structure with a first width and a second, differing, width.

Abstract: A method of fabricating a semiconductor device is illustrated. A modified profile opening is formed on a substrate. The modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate. The second width is greater than the first width. A metal gate electrode is formed by filling the modified profile opening with a conductive material. A semiconductor device is also described, the device having a metal gate structure with a first width and a second, differing, width.

Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.

Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.

Abstract: An method of fabricating the gate structure comprises: sequentially depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a nitrogen-containing dielectric layer and an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer by exposing a surface of the dummy oxide layer to a vapor mixture comprising NH3 and a fluorine-containing compound at a first temperature; heating the substrate to a second temperature to form an opening in the nitrogen-containing dielectric layer; depositing a gate dielectric; and depositing a gate electrode.

Abstract: Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.

Abstract: Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.

Abstract: Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes the conductive liner contacting the portion of the surface of the first conductive layer. A trench structure is formed on the via structure in the dielectric without the conductive liner layer in the trench.

Abstract: A box-spring assembly includes two frames, a resilient member, a plurality of lateral springs, and a plurality of clips. The frames are spaced apart from each other, and each of the frames has a looped lateral frame rod. The resilient member includes an array of spring coil units disposed between the frames, and a plurality of connecting elements connecting the spring coil units to each other. Each of the lateral springs is connected between the looped lateral frame rods so as to reinforce the looped lateral frame rods. The clips connect the spring coil units and the lateral springs to the looped lateral frame rods.