Patents by Inventor Yiheng Xu
Yiheng Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10950722Abstract: Vertical GAA FET structures are disclosed in which a current-carrying nanowire is oriented substantially perpendicular to the surface of a silicon substrate. The vertical GAA FET is intended to meet design and performance criteria for the 7 nm technology generation. In some embodiments, electrical contacts to the drain and gate terminals of the vertically oriented GAA FET can be made via the backside of the substrate. Examples are disclosed in which various n-type and p-type transistor designs have different contact configurations. In one example, a backside gate contact extends through the isolation region between adjacent devices. Other embodiments feature dual gate contacts for circuit design flexibility. The different contact configurations can be used to adjust metal pattern density.Type: GrantFiled: December 31, 2014Date of Patent: March 16, 2021Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John H. Zhang, Carl Radens, Lawrence A. Clevenger, Yiheng Xu
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Patent number: 10832965Abstract: Integrated circuit devices include trenches in a material layer that divide the material layer into fins. With such devices, an insulator partially fills the trenches and contacts the material layer. The top surface of the insulator (e.g., the surface opposite where the insulator contacts the material layer) has a convex dome shape between at least two of the fins. The dome shape has a first thickness from (from the bottom of the trench) where the insulator contacts the fins, and a second thickness that is greater than the first thickness where the insulator is between the fins. Further, there is a maximum thickness difference between the first and second thicknesses at the midpoint between the fins (e.g., the highest point of the dome shape is at the midpoint between the fins). Also, the top surface of the first insulator has concave divots where the first insulator contacts the fins.Type: GrantFiled: January 11, 2018Date of Patent: November 10, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Yiheng Xu, Haiting Wang, Qun Gao, Scott Beasor, Kyung Bum Koo, Ankur Arya
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Patent number: 10790198Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fin structures and methods of manufacture. The structure includes: a plurality of fin structures formed of substrate material; a semiconductor material located between selected fin structures of the plurality of fin structures; and isolation regions within spaces between the plurality of fin structures.Type: GrantFiled: August 8, 2018Date of Patent: September 29, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Fuad H. Al-Amoody, Yiheng Xu, Rishikesh Krishnan
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Patent number: 10700214Abstract: Processes and overturned thin film device structures generally include a gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the gate and the source/drain contacts include a self-aligned step height.Type: GrantFiled: April 5, 2018Date of Patent: June 30, 2020Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
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Publication number: 20200051867Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fin structures and methods of manufacture. The structure includes: a plurality of fin structures formed of substrate material; a semiconductor material located between selected fin structures of the plurality of fin structures; and isolation regions within spaces between the plurality of fin structures.Type: ApplicationFiled: August 8, 2018Publication date: February 13, 2020Inventors: Fuad H. AL-AMOODY, Yiheng XU, Rishikesh KRISHNAN
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Patent number: 10546743Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect process incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.Type: GrantFiled: January 18, 2018Date of Patent: January 28, 2020Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John H. Zhang, Yann Mignot, Lawrence A. Clevenger, Carl Radens, Richard Stephen Wise, Yiheng Xu, Yannick Loquet, Hsueh-Chung Chen
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Publication number: 20200011821Abstract: This invention addressed a method for measuring the foreign substance content invaded into a thin plate porous material based on the principle of virtual heat sources. The technical points of the invention are: (1) using the principle of virtual heat sources to improve the traditional heat pulse method to measure the foreign substance content; (2) representing the heat transfer effect on boundaries of the thin plate porous material by establishing an infinite number of virtual heat sources with two different heat intensities; (3) obtaining the volumetric heat capacity of the test material together with the invaded foreign substance content based on the four-parameter search to obtain the best temperature match between the measurement and the solution.Type: ApplicationFiled: May 28, 2018Publication date: January 9, 2020Inventors: Tengfei ZHANG, Yiheng XU, Shugang WANG, Jihong WANG
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Patent number: 10388639Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by theType: GrantFiled: November 3, 2017Date of Patent: August 20, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
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Patent number: 10361289Abstract: A method of thermally oxidizing a Si fin to form an oxide layer over the Si fin and then forming an ALD oxide layer over the oxide layer and resulting device are provided. Embodiments include forming a plurality of Si fins on a Si substrate; forming a dielectric layer over the plurality of Si fins and the Si substrate; recessing the dielectric layer, exposing a top portion of the plurality of Si fins; thermally oxidizing surface of the top portion of the plurality of Si fins, an oxide layer formed; and forming an ALD oxide layer over the oxide layer.Type: GrantFiled: March 22, 2018Date of Patent: July 23, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Wei Zhao, Shahab Siddiqui, Haiting Wang, Ting-Hsiang Hung, Yiheng Xu, Beth Baumert, Jinping Liu, Scott Beasor, Yue Zhong, Shesh Mani Pandey
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Publication number: 20190214308Abstract: Integrated circuit devices include trenches in a material layer that divide the material layer into fins. With such devices, an insulator partially fills the trenches and contacts the material layer. The top surface of the insulator (e.g., the surface opposite where the insulator contacts the material layer) has a convex dome shape between at least two of the fins. The dome shape has a first thickness from (from the bottom of the trench) where the insulator contacts the fins, and a second thickness that is greater than the first thickness where the insulator is between the fins. Further, there is a maximum thickness difference between the first and second thicknesses at the midpoint between the fins (e.g., the highest point of the dome shape is at the midpoint between the fins). Also, the top surface of the first insulator has concave divots where the first insulator contacts the fins.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Yiheng Xu, Haiting Wang, Qun Gao, Scott Beasor, Kyung Bum Koo, Ankur Arya
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Patent number: 10347617Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by theType: GrantFiled: September 5, 2017Date of Patent: July 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
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Patent number: 10319630Abstract: A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers.Type: GrantFiled: September 27, 2012Date of Patent: June 11, 2019Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
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Patent number: 10304815Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by theType: GrantFiled: November 3, 2017Date of Patent: May 28, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
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Patent number: 10211045Abstract: An insulator is formed by flowable chemical vapor deposition (FCVD) process. The insulator is cured by exposing the insulator to ultraviolet light while flowing ozone over the insulator to produce a cured insulator. The curing process forms nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters in the insulator. Following the curing process, these methods select wavelengths of microwave radiation (that will be subsequently used during annealing) so that such wavelengths excite the nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters. Then, these methods anneal the cured insulator by exposing the cured insulator to microwave radiation in an inert (e.g., non-oxidizing) ambient atmosphere, at a temperature below 500° C., so as to increase the density of the cured insulator.Type: GrantFiled: January 24, 2018Date of Patent: February 19, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Rishikesh Krishnan, Joseph K. Kassim, Bharat V. Krishnan, Joseph F. Shepard, Jr., Rinus Tek Po Lee, Yiheng Xu
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Publication number: 20190027556Abstract: A method of forming a shallow trench isolation (STI) for an integrated circuit (IC) structure to mitigate fin bending disclosed. The method may include forming a first insulator layer in a first portion of an opening in a substrate by a bottom-up atomic layer deposition (ALD) process; and forming a second insulator layer on the first insulator layer in a second portion of the opening. The opening may be position between a set of fins in the substrate. The method may further include forming an oxide liner in the opening before the forming the first insulator layer. The second insulator layer may be formed by deposition using a flowable chemical vapor deposition (FCVD) process, high aspect ratio process (HARP), high-density plasma chemical vapor deposition (HDP CVD) process, or any other conventional insulator material deposition process.Type: ApplicationFiled: July 21, 2017Publication date: January 24, 2019Inventors: Jiehui Shu, Rishikesh Krishnan, Jinping Liu, Yiheng Xu, Joseph F. Shepard, JR.
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Publication number: 20180226511Abstract: Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the metal gate and the contacts can be self-aligned to the sacrificial material.Type: ApplicationFiled: April 5, 2018Publication date: August 9, 2018Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
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Patent number: 10026849Abstract: Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the metal gate and the contacts can be self-aligned to the sacrificial material.Type: GrantFiled: September 8, 2016Date of Patent: July 17, 2018Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
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Patent number: 9984933Abstract: A hardmask is patterned on a first material to leave hardmask elements. The first material is patterned into fins through the hardmask. A layer of silicon is formed on the hardmask elements and the fins in processing that forms the layer of silicon thicker on the hardmask elements relative to the fins. An isolation material is formed on the layer of silicon to leave the isolation material filling spaces between the fins. The isolation material and the layer of silicon are annealed to consume relatively thinner portions of the layer of silicon and leave the layer of silicon on the hardmask elements as silicon elements. A chemical mechanical polishing (CMP) is performed on the isolation material to make the isolation material planar with the silicon elements. A first etching agent removes the silicon elements on the hardmask elements, and a second chemical agent removes the hardmask elements.Type: GrantFiled: October 3, 2017Date of Patent: May 29, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Yiheng Xu, Haiting Wang, Wei Zhao, Todd B. Abrams, Jiehui Shu, Jinping Liu, Scott Beasor
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Publication number: 20180144926Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect process incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.Type: ApplicationFiled: January 18, 2018Publication date: May 24, 2018Inventors: John H. Zhang, Yann Mignot, Lawrence A. Clevenger, Carl Radens, Richard Stephen Wise, Yiheng Xu, Yannick Loquet, Hsueh-Chung Chen
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Publication number: 20180068994Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by theType: ApplicationFiled: November 3, 2017Publication date: March 8, 2018Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang