Patents by Inventor Yiheng Xu
Yiheng Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20180061817Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by theType: ApplicationFiled: November 3, 2017Publication date: March 1, 2018Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
-
Patent number: 9905511Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.Type: GrantFiled: November 10, 2015Date of Patent: February 27, 2018Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John H. Zhang, Yiheng Xu, Lawrence A. Clevenger, Carl Radens, Edem Wornyo
-
Publication number: 20170365590Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by theType: ApplicationFiled: September 5, 2017Publication date: December 21, 2017Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
-
Patent number: 9837394Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by theType: GrantFiled: December 2, 2015Date of Patent: December 5, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
-
Patent number: 9786551Abstract: An integrated circuit includes a substrate with an interlevel dielectric layer positioned above the substrate. First trenches having a first depth are formed in the interlevel dielectric layer and a metal material fills the first trenches to form first interconnection lines. Second trenches having a second depth are also formed in the interlevel dielectric layer and filled with a metal material to form second interconnection lines. The first and second interconnection lines have a substantially equal pitch, which in a preferred implementation is a sub-lithographic pitch, and different resistivities due to the difference in trench depth. The first and second trenches are formed with an etching process through a hard mask having corresponding first and second openings of different depths. A sidewall image transfer process is used to define sub-lithographic structures for forming the first and second openings in the hard mask.Type: GrantFiled: April 29, 2014Date of Patent: October 10, 2017Assignees: STMICROELECTRONICS, INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Hongguang Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard Stephen Wise
-
Publication number: 20170162554Abstract: Self-aligned three dimensional vertically stacked chip stacks and processes for forming the same generally include two or more vertically stacked chips supported by a scaffolding structure, the scaffolding structure defined by a first scaffolding trench and at least one additional scaffolding trench, the first scaffolding trench comprising a bottom surface having a width and a sidewall having a height extending from the bottom surface to define a lowermost trench in a scaffolding layer, the at least one additional scaffolding trench overlaying the first scaffolding trench having a sidewall having a height and a width, wherein the width of the at least one scaffolding trench is greater than the first scaffolding trench width to define a first stair between the first scaffolding trench and the at least one additional trench; a first chip secured to the first scaffolding trench having a height less than the first scaffolding trench sidewall height; and at least one additional chip secured to and supported by theType: ApplicationFiled: December 2, 2015Publication date: June 8, 2017Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
-
Publication number: 20170162711Abstract: Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the metal gate and the contacts can be self-aligned to the sacrificial material.Type: ApplicationFiled: September 8, 2016Publication date: June 8, 2017Inventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
-
Patent number: 9659820Abstract: A method of forming a wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.Type: GrantFiled: May 2, 2016Date of Patent: May 23, 2017Assignees: International Business Machines Corporation, STMICROELECTRONICS, INC.Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard Stephen Wise, Akil K. Sutton, Terry Allen Spooner, Nicole A. Saulnier
-
Patent number: 9658523Abstract: A wavy line interconnect structure that accommodates small metal lines and large vias is disclosed. A lithography mask design used to pattern metal line trenches uses optical proximity correction (OPC) techniques to approximate wavy lines using rectangular opaque features. The large vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. Instead, a sacrificial layer allows etching of an underlying thick dielectric block, while protecting narrow features of the trenches that correspond to the metal line interconnects. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By lifting the shrink constraint for vias, thereby allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.Type: GrantFiled: March 31, 2014Date of Patent: May 23, 2017Assignees: STMicroelectronics, Inc., International Business Machines CorporationInventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard Stephen Wise, Terry Spooner, Nicole A. Saulnier
-
Patent number: 9646939Abstract: Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the edges of a die to prevent and detect damages to the die. The multilayer structure includes a support layer, a first plurality of dielectric pillars overlying the support layer, a metal layer that fills spaces between the first plurality of dielectric pillars, an insulation layer overlying the first plurality of dielectric pillars and the metal layer, a second plurality of dielectric pillars overlying the insulation layer, and a second metal layer that fills spaces between the second plurality of dielectric pillars.Type: GrantFiled: April 5, 2016Date of Patent: May 9, 2017Assignees: International Business Machines Corporation, STMicroelectronics, Inc.Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Byoung Youp Kim, Walter Kleemeier
-
Patent number: 9633986Abstract: A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.Type: GrantFiled: June 7, 2016Date of Patent: April 25, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Edem Wornyo
-
Patent number: 9502325Abstract: A structure and method for fabricating a continuous cooling channel in the back end of line wiring levels of an integrated circuit (IC) chip is provided. This continuous cooling channel may provide a path for a cooling source such as a fluid pumped from an external fluidic-cooling circulation driver to make physical contact locally with and cool the back end levels within the IC chip that may generate heat as a byproduct of the IC device's routine operations. Such a cooling structure is achieved by removing a horizontal portion of a barrier layer from an intermediate region of an interlevel interconnect structure, selective to a vertical portion of the barrier layer located on a sidewall of the interlevel interconnect structure, using gas cluster ion beam etching as well as removing the bulk conductor by additional means.Type: GrantFiled: May 19, 2016Date of Patent: November 22, 2016Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Vincent J. McGahay, Joyeeta Nag, Yiheng Xu
-
Patent number: 9496415Abstract: Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the metal gate and the contacts can be self-aligned to the sacrificial material.Type: GrantFiled: December 2, 2015Date of Patent: November 15, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu, John H. Zhang
-
Publication number: 20160293589Abstract: A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits.Type: ApplicationFiled: June 7, 2016Publication date: October 6, 2016Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Edem Wornyo
-
Publication number: 20160254208Abstract: A structure and method for fabricating a continuous cooling channel in the back end of line wiring levels of an integrated circuit (IC) chip is provided. This continuous cooling channel may provide a path for a cooling source such as a fluid pumped from an external fluidic-cooling circulation driver to make physical contact locally with and cool the back end levels within the IC chip that may generate heat as a byproduct of the IC device's routine operations. Such a cooling structure is achieved by removing a horizontal portion of a barrier layer from an intermediate region of an interlevel interconnect structure, selective to a vertical portion of the barrier layer located on a sidewall of the interlevel interconnect structure, using gas cluster ion beam etching as well as removing the bulk conductor by additional means.Type: ApplicationFiled: May 19, 2016Publication date: September 1, 2016Inventors: Lawrence A. Clevenger, Vincent J. McGahay, Joyeeta Nag, Yiheng Xu
-
Publication number: 20160247722Abstract: A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.Type: ApplicationFiled: May 2, 2016Publication date: August 25, 2016Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard Stephen Wise, Akil K. Sutton, Terry Allen Spooner, Nicole A. Saulnier
-
Patent number: 9412654Abstract: After forming a copper seed layer on a diffusion barrier layer present on sidewalls and a bottom surface of at least one opening, a graphene sacrificial layer is deposited over the copper seed layer before the copper seed layer is exposed to an environment that oxidizes the copper seed layer, thus providing process flexibility for longer queue times (Q-times) between copper seed layer deposition and copper plating. Next, the graphene sacrificial layer is subjected to a plasma treatment to introduce disorders and defects into the graphene sacrificial layer for removal just before the copper plating. The entire structure is then immersed in a copper plating solution. The copper plating solution dissolves the plasma treated graphene sacrificial layer and forms a copper-containing layer on the re-exposed copper seed layer.Type: GrantFiled: April 27, 2015Date of Patent: August 9, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Junjing Bao, Lawrence A. Clevenger, Vincent J. McGahay, Joyeeta Nag, Richard S. Wise, Yiheng Xu
-
Publication number: 20160218070Abstract: Various embodiments facilitate die protection for an integrated circuit. In one embodiment, a multilayer structure is formed in multiple levels and along the edges of a die to prevent and detect damages to the die. The multilayer structure includes a support layer, a first plurality of dielectric pillars overlying the support layer, a metal layer that fills spaces between the first plurality of dielectric pillars, an insulation layer overlying the first plurality of dielectric pillars and the metal layer, a second plurality of dielectric pillars overlying the insulation layer, and a second metal layer that fills spaces between the second plurality of dielectric pillars.Type: ApplicationFiled: April 5, 2016Publication date: July 28, 2016Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Byoung Youp Kim, Walter Kleemeier
-
Patent number: 9391020Abstract: A wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. An interconnect structure having enlarged diameter vias can also feature air gaps to reduce the chance of dielectric breakdown. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm.Type: GrantFiled: June 25, 2014Date of Patent: July 12, 2016Assignees: STMicroelectronics, Inc., International Business Machines CorporationInventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Richard Stephen Wise, Akil K. Sutton, Terry Allen Spooner, Nicole A. Saulnier
-
Patent number: 9385177Abstract: A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method of fabricating such a structure cleverly takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers.Type: GrantFiled: October 31, 2013Date of Patent: July 5, 2016Assignees: STMicroelectronics, Inc., International Business Machines CorporationInventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Edem Wornyo