Patents by Inventor Yiheng Xu

Yiheng Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8921976
    Abstract: Passive circuit elements are formed at surfaces of two integrated circuit wafers. The passive circuit elements are utilized to align the two integrated circuit wafers to form an integrated circuit wafer stack.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: December 30, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Yiheng Xu
  • Patent number: 8900990
    Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: December 2, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Walter Kleemeier, Cindy Goldberg
  • Patent number: 8889506
    Abstract: An integrated circuit die includes a semiconductor substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer. Trenches are formed in the first and second dielectric layers. Metal interconnection tracks are formed on sidewalls of the trench on the exposed portions of the second dielectric layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: November 18, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Edem Wornyo
  • Patent number: 8859350
    Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 14, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Yiheng Xu, Carl Radens, Lawrence A. Clevenger
  • Patent number: 8829670
    Abstract: The present disclosure is directed to a device that includes a first substrate having a first plurality of hollow pillars on the first substrate and a first plurality of channels in the first substrate coupled to the first plurality of hollow pillars. The device includes a second substrate attached to the first substrate, the second substrate having a second plurality of hollow pillars on the second substrate and a second plurality of channels in the second substrate coupled to the second plurality of hollow pillars, the first plurality of hollow pillars being coupled to the second plurality of hollow pillars to allow a fluid medium to move through the substrate to cool the first substrate and the second substrate.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: September 9, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu, Edem Wornyo
  • Publication number: 20140183735
    Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: John H. ZHANG, Lawrence A. Clevenger, Carl Radens, Yiheng XU, Walter Kleemeier, Cindy Goldberg
  • Publication number: 20140175610
    Abstract: A junction diode array for use in protecting integrated circuits from electrostatic discharge can be fabricated to include symmetric and/or asymmetric junction diodes of various sizes. The diodes can be configured to provide low voltage and current discharge via unencapsulated contacts, or high voltage and current discharge via encapsulated contacts. Use of tilted implants in fabricating the junction diode array allows a single hard mask to be used to implant multiple ion species. Furthermore, a different implant tilt angle can be chosen for each species, along with other parameters, (e.g., implant energy, implant mask thickness, and dimensions of the mask openings) so as to craft the shape of the implanted regions. Isolation regions can be inserted between already formed diodes, using the same implant hard mask if desired. A buried oxide layer can be used to prevent diffusion of dopants into the substrate beyond a selected depth.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
  • Publication number: 20140134808
    Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.
    Type: Application
    Filed: January 17, 2014
    Publication date: May 15, 2014
    Applicants: International Business Machines Corporation, STMicroelectronics, Inc.
    Inventors: John H. Zhang, Yiheng Xu, Carl Radens, Lawrence A. Clevenger
  • Publication number: 20140099787
    Abstract: A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer; transferring the wiring pattern through the lower antireflective coating layer; and transferring the wiring pattern through the dielectric layer, wherein unpatterned portions of the lower antireflective coating layer serve as an etch stop layer so as to prevent any bubble defects present in the organic planarizing layer from being transferred to the dielectric layer.
    Type: Application
    Filed: October 10, 2012
    Publication date: April 10, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas W. Dyer, Hanako Henry, Tze-Man Ko, Yiheng Xu, Shaoning Yao
  • Patent number: 8685850
    Abstract: According to one embodiment of the invention, the gate contact is formed by a selective deposition on the gate electrode. One acceptable technique for the selective deposition is by plating. Plating is one process by which a metal structure, such as a gate contact, may be formed directly on the gate electrode. The plating is carried out by immersing the semiconductor die in a plating solution with the gate electrode exposed. The gate contact is plated onto the gate electrode and thus is ensured of being fully aligned exactly to the gate electrode. After this, the appropriate dielectric layers are formed adjacent the gate contact and over the source and drain to ensure that the gate electrode is electrically isolated from other components of the transistor.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: April 1, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl J. Radens, Yiheng Xu
  • Publication number: 20140084481
    Abstract: A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
  • Publication number: 20140084465
    Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
  • Patent number: 8680577
    Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: March 25, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: John H. Zhang, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
  • Patent number: 8623673
    Abstract: A test structure and method for monitoring process uniformity. Embodiments of the invention include test structures having a first metallization layer, a second metallization layer formed above the first metallization layer, a defect-generating region in a first metallization layer, a defect-dispersing region in the second metallization layer above the defect-generating region; and a defect-detecting region in the second metallization layer adjacent to the defect-dispersing region. The defect-generating region of the exemplary embodiment may have zero pattern density, uniform non-zero pattern density, or non-uniform non-zero pattern density. The defect-detecting region may include a test pattern such as, a comb-serpentine structure. Embodiments may include more than one defect-generating region, more than one defect-dispersing region, or more than one defect-detecting region.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Tze-Man Ko, Yiheng Xu, Shaoning Yao
  • Patent number: 8395228
    Abstract: A method of improving the focus leveling response of a semiconductor wafer is described. The method includes combining organic and inorganic or metallic near infrared (NIR) hardmask on a semiconductor substrate; forming an anti-reflective coating (ARC) layer on the combined organic NIR-absorption and the inorganic or metallic NIR-absorption hardmask; and forming a photoresist layer on the ARC layer. A semiconductor structure is also described including a substrate, a resist layer located over the structure; and an absorptive layer located over the substrate. The absorptive layer includes an inorganic or metallic NIR-absorbing hardmask layer.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: March 12, 2013
    Assignee: International Business Machines Corporation
    Inventors: Wai-Kin Li, Wu-Song Huang, Dario Leonardo Goldfarb, Martin Glodde, Edward Engbrecht, Yiheng Xu
  • Publication number: 20120313144
    Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.
    Type: Application
    Filed: June 12, 2012
    Publication date: December 13, 2012
    Applicants: International Business Machines, STMicroelectronics, Inc.
    Inventors: John H. ZHANG, Lawrence A. Clevenger, Carl Radens, Yiheng Xu
  • Publication number: 20120313153
    Abstract: According to one embodiment of the invention, the gate contact is formed by a selective deposition on the gate electrode. One acceptable technique for the selective deposition is by plating. Plating is one process by which a metal structure, such as a gate contact, may be formed directly on the gate electrode. The plating is carried out by immersing the semiconductor die in a plating solution with the gate electrode exposed. The gate contact is plated onto the gate electrode and thus is ensured of being fully aligned exactly to the gate electrode. After this, the appropriate dielectric layers are formed adjacent the gate contact and over the source and drain to ensure that the gate electrode is electrically isolated from other components of the transistor.
    Type: Application
    Filed: June 12, 2012
    Publication date: December 13, 2012
    Applicants: INTERNATIONAL BUSINESS MACHINES, STMICROELECTRONICS, INC.
    Inventors: John H. ZHANG, Lawrence A. CLEVENGER, Carl J. RADENS, Yiheng XU
  • Publication number: 20120187530
    Abstract: Passive circuit elements are formed at surfaces of two integrated circuit wafers. The passive circuit elements are utilized to align the two integrated circuit wafers to form an integrated circuit wafer stack.
    Type: Application
    Filed: December 13, 2011
    Publication date: July 26, 2012
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: John H. Zhang, Lawrence A. Clevenger, Yiheng Xu
  • Publication number: 20120112302
    Abstract: A method of improving the focus leveling response of a semiconductor wafer is described. The method includes combining organic and inorganic or metallic near infrared (NIR) hardmask on a semiconductor substrate; forming an anti-reflective coating (ARC) layer on the combined organic NIR-absorption and the inorganic or metallic NIR-absorption hardmask; and forming a photoresist layer on the ARC layer. A semiconductor structure is also described including a substrate, a resist layer located over the structure; and an absorptive layer located over the substrate. The absorptive layer includes an inorganic or metallic NIR-absorbing hardmask layer.
    Type: Application
    Filed: November 8, 2010
    Publication date: May 10, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wai-Kin Li, Wu-Song Huang, Dario Leonardo Goldfarb, Martin Glodde, Edward Engbrecht, Yiheng Xu
  • Patent number: 8026166
    Abstract: Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiwCxNyHz disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiwCxNyHz disposed upon the second capping layer, wherein a+b+c+d=1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w+x+y+z=1.0 and w, x, y, and z are each greater than 0 and less than 1.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: September 27, 2011
    Assignees: International Business Machines Corporation, Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing Ltd.
    Inventors: Griselda Bonilla, Tien Cheng, Lawrence A. Clevenger, Stephan Grunow, Chao-Kun Hu, Roger A. Quon, Zhiguo Sun, Wei-tsui Tseng, Yiheng Xu, Yun Wang, Hyeok-sang Oh