Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect structure incorporates deep air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of a deep air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the deep air gap is used as an insulator and a means of reducing fringe capacitance between adjacent metal lines. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

Abstract: A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method of fabricating such a structure cleverly takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers.

Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.

Abstract: A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer; transferring the wiring pattern through the lower antireflective coating layer; and transferring the wiring pattern through the dielectric layer, wherein unpatterned portions of the lower antireflective coating layer serve as an etch stop layer so as to prevent any bubble defects present in the organic planarizing layer from being transferred to the dielectric layer.

Abstract: A method of forming an integrated circuit structure includes forming a cap layer above a first ILD layer of a first metal level, the first ILD layer includes a recess filled with a first conductive material to form a first interconnect structure. Next, a second ILD layer is formed above the cap layer and a via is formed within the second ILD layer as a second interconnect structure of a second metal level. The via is aligned with the first interconnect structure. Subsequently, a portion of the cap layer is removed to extend the via to expose a top portion of the first conductive material then a passivation cap is selectively formed at a bottom portion of the via in the second ILD layer and the passivation cap contacting the top portion of the first conductive material. The passivation cap includes a metal alloy to form an interface between the bottom portion of the via and the first conductive material.

Abstract: A junction diode array is disclosed for use in protecting integrated circuits from electrostatic discharge. The junction diodes integrate symmetric and asymmetric junction diodes of various sizes and capabilities. Some of the junction diodes are configured to provide low voltage and current discharge via un-encapsulated interconnecting wires, while others are configured to provide high voltage and current discharge via encapsulated interconnecting wires. Junction diode array elements include p-n junction diodes and N+/N++ junction diodes. The junction diodes include implanted regions having customized shapes. If both symmetric and asymmetric diodes are not needed as components of the junction diode array, the array is configured with isolation regions between diodes of either type. Some junction diode arrays include a buried oxide layer to prevent diffusion of dopants into the substrate beyond a selected depth.

Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.

Abstract: Passive circuit elements are formed at surfaces of two integrated circuit wafers. The passive circuit elements are utilized to align the two integrated circuit wafers to form an integrated circuit wafer stack.

Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.

Abstract: An integrated circuit die includes a semiconductor substrate, a first dielectric layer on the substrate, and a second dielectric layer on the first dielectric layer. Trenches are formed in the first and second dielectric layers. Metal interconnection tracks are formed on sidewalls of the trench on the exposed portions of the second dielectric layer.

Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

Abstract: The present disclosure is directed to a device that includes a first substrate having a first plurality of hollow pillars on the first substrate and a first plurality of channels in the first substrate coupled to the first plurality of hollow pillars. The device includes a second substrate attached to the first substrate, the second substrate having a second plurality of hollow pillars on the second substrate and a second plurality of channels in the second substrate coupled to the second plurality of hollow pillars, the first plurality of hollow pillars being coupled to the second plurality of hollow pillars to allow a fluid medium to move through the substrate to cool the first substrate and the second substrate.

Abstract: Metal interconnections are formed in an integrated by combining damascene processes and subtractive metal etching. A wide trench is formed in a dielectric layer. A conductive material is deposited in the wide trench. Trenches are etched in the conductive material to delineate a plurality of metal plugs each contacting a respective metal track exposed by the wide trench.

Abstract: A junction diode array for use in protecting integrated circuits from electrostatic discharge can be fabricated to include symmetric and/or asymmetric junction diodes of various sizes. The diodes can be configured to provide low voltage and current discharge via unencapsulated contacts, or high voltage and current discharge via encapsulated contacts. Use of tilted implants in fabricating the junction diode array allows a single hard mask to be used to implant multiple ion species. Furthermore, a different implant tilt angle can be chosen for each species, along with other parameters, (e.g., implant energy, implant mask thickness, and dimensions of the mask openings) so as to craft the shape of the implanted regions. Isolation regions can be inserted between already formed diodes, using the same implant hard mask if desired. A buried oxide layer can be used to prevent diffusion of dopants into the substrate beyond a selected depth.

Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

Abstract: A method of forming an interconnect structure for a semiconductor device includes forming a lower antireflective coating layer over a dielectric layer; forming an organic planarizing layer on the lower antireflective coating layer; transferring a wiring pattern through the organic planarizing layer; transferring the wiring pattern through the lower antireflective coating layer; and transferring the wiring pattern through the dielectric layer, wherein unpatterned portions of the lower antireflective coating layer serve as an etch stop layer so as to prevent any bubble defects present in the organic planarizing layer from being transferred to the dielectric layer.

Abstract: According to one embodiment of the invention, the gate contact is formed by a selective deposition on the gate electrode. One acceptable technique for the selective deposition is by plating. Plating is one process by which a metal structure, such as a gate contact, may be formed directly on the gate electrode. The plating is carried out by immersing the semiconductor die in a plating solution with the gate electrode exposed. The gate contact is plated onto the gate electrode and thus is ensured of being fully aligned exactly to the gate electrode. After this, the appropriate dielectric layers are formed adjacent the gate contact and over the source and drain to ensure that the gate electrode is electrically isolated from other components of the transistor.

Abstract: A plurality of metal tracks are formed in an integrated circuit die in three metal layers stacked within the die. A protective dielectric layer is formed around metal tracks of an intermediate metal layer. The protective dielectric layer acts as a hard mask to define contact vias between metal tracks in the metal layers above and below the intermediate metal layer.

Abstract: A plurality of metal tracks are formed in a plurality of intermetal dielectric layers stacked in an integrated circuit die. Thin protective dielectric layers are formed around the metal tracks. The protective dielectric layers act as a hard mask to define contact vias between metal tracks in the intermetal dielectric layers.

Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.