Patents by Inventor Yikang Deng

Yikang Deng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210391263
    Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.
    Type: Application
    Filed: June 16, 2020
    Publication date: December 16, 2021
    Applicant: Intel Corporation
    Inventors: Bai Nie, Gang Duan, Omkar G. Karhade, Nitin A. Deshpande, Yikang Deng, Wei-Lun Jen, Tarek A. Ibrahim, Sri Ranga Sai Boyapati, Robert Alan May, Yosuke Kanaoka, Robin Shea McRee, Rahul N. Manepalli
  • Publication number: 20210304952
    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 30, 2021
    Inventors: William J. Lambert, Mihir K. Roy, Mathew J. Manusharow, Yikang Deng
  • Publication number: 20210307172
    Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.
    Type: Application
    Filed: September 2, 2016
    Publication date: September 30, 2021
    Applicant: INTEL CORPORATION
    Inventors: Kristof Darmawikarta, Robert A. May, Yikang Deng, Ji Yong Park, Maroun D. Moussallem, Amruthavalli P. Alur, Sri Ranga Sai Boyapati, Lilia May
  • Publication number: 20210305154
    Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a magnetic structure around the conductive line, and material stubs at side faces of the magnetic structure.
    Type: Application
    Filed: March 25, 2020
    Publication date: September 30, 2021
    Applicant: Intel Corporation
    Inventors: Ying Wang, Yikang Deng, Junnan Zhao, Andrew James Brown, Cheng Xu, Kaladhar Radhakrishnan
  • Publication number: 20210273036
    Abstract: An integrated circuit (IC) package substrate, comprising a magnetic material embedded within a dielectric material. A first surface of the dielectric material is below the magnetic material, and a second surface of the dielectric material, opposite the first surface, is over the magnetic material. A metallization level comprising a first metal feature is embedded within the magnetic material. A second metal feature is at an interface of the magnetic material and the dielectric material. The second metal feature has a first sidewall in contact with the dielectric material and a second sidewall in contact with the magnetic material.
    Type: Application
    Filed: February 28, 2020
    Publication date: September 2, 2021
    Applicant: Intel Corporation
    Inventors: Brandon C. Marin, Tarek Ibrahim, Prithwish Chatterjee, Haifa Hariri, Yikang Deng, Sheng C. Li, Srinivas Pietambaram
  • Patent number: 11031360
    Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Yikang Deng, Kyu Oh Lee, Ji Yong Park, Srinivas Pietambaram, Ying Wang, Chong Zhang, Rui Zhang, Junnan Zhao
  • Patent number: 10998120
    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: William J. Lambert, Mihir K Roy, Mathew J Manusharow, Yikang Deng
  • Publication number: 20210020558
    Abstract: An electronic device may include a substrate, and the substrate may include one or more layers. The one or more layers may include a first dielectric material and one or more electrical traces. A cavity may be defined in the substrate, and the cavity may be adapted to receive one or more electrical components. One or more lateral traces may extend through a wall of the cavity. The lateral traces may provide electrical communication pathways between the substrate and the electrical components.
    Type: Application
    Filed: October 6, 2020
    Publication date: January 21, 2021
    Inventors: Yikang Deng, Ying Wang, Cheng Xu, Chong Zhang, Junnan Zhao
  • Publication number: 20200411413
    Abstract: A substrate for an electronic device may include a first layer, and the first layer may include dielectric material. The first layer may include a first interconnect, and the first interconnect may have a first interconnect profile. The substrate may include a second layer, and the second layer may include dielectric material. The second layer may include a second interconnect, and the second interconnect may have a second interconnect profile. The first interconnect profile may be indicative of a subtractive manufacturing operation and the second interconnect profile may be indicative of an additive manufacturing operation.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Amruthavalli Pallavi Alur, Brandon C. Marin, Yikang Deng, Liwei Cheng, Jeremy D. Ecton, Andrew J. Brown, Lauren A. Link, Cheng Xu, Prithwish Chatterjee, Ying Wang
  • Publication number: 20200373257
    Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.
    Type: Application
    Filed: August 11, 2020
    Publication date: November 26, 2020
    Inventors: Cheng Xu, Yikang Deng, Kyu Oh Lee, Ji Yong Park, Srinivas Venkata Ramanuja Pietambaram, Ying Wang, Chong Zhang, Rui Zhang, Junnan Zhao
  • Patent number: 10845552
    Abstract: An optoelectronic apparatus is presented. In embodiments, the apparatus may include a package including a substrate with a first side and a second side opposite the first side, wherein the first side comprises a ball grid array (BGA) field. The apparatus may further include one or more integrated circuits (ICs) disposed on the first side of the substrate, inside the BGA field, that thermally interface with a printed circuit board (PCB), to which the package is to be coupled, one or more optical ICs coupled to the second side and communicatively coupled with the one or more ICs via interconnects provided in the substrate, wherein at least one of the optical ICs is at least partially covered by an integrated heat spreader (IHS), to provide dissipation of heat produced by the at least one optical IC.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Henning Braunisch, Timothy A. Gosselin, Prasanna Raghavan, Yikang Deng, Zhiguo Qian
  • Patent number: 10804188
    Abstract: An electronic device may include a substrate, and the substrate may include one or more layers. The one or more layers may include a first dielectric material and one or more electrical traces. A cavity may be defined in the substrate, and the cavity may be adapted to receive one or more electrical components. One or more lateral traces may extend through a wall of the cavity. The lateral traces may provide electrical communication pathways between the substrate and the electrical components.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Yikang Deng, Ying Wang, Cheng Xu, Chong Zhang, Junnan Zhao
  • Publication number: 20200312738
    Abstract: An integrated circuit assembly may be formed having at least one integrated circuit device electrically attached to an electronic substrate. The integrated circuit assembly may further include at least one heat dissipation device attached to the electronic substrate, wherein the at least one heat dissipation device comprises a phase change material within a containment chamber. The at least one integrated circuit device may be thermally connected to the at least one heat dissipation device with at least one heat transfer structure formed in or on the electronic substrate.
    Type: Application
    Filed: March 26, 2019
    Publication date: October 1, 2020
    Applicant: Intel Corporation
    Inventors: Junnan Zhao, Cheng Xu, Zhimin Wan, Yikang Deng, Chong Zhang, Ying Wang
  • Patent number: 10790159
    Abstract: The systems and methods described herein provide for the fabrication of semiconductor package substrates having magnetic inductors formed in at least a portion of the through-holes formed in the semiconductor package substrate. Such magnetic inductors are formed without exposing the magnetic material disposed in the through-hole to any wet chemistry (desmear, electro-less plating, etc.) processes by sealing the magnetic material with a patterned sealant (e.g., patterned dry film resist) which seals the magnetic material prior to performing steps involving wet chemistry on the semiconductor package substrate. Such beneficially minimizes or even eliminates the contamination of wet chemistry reagents by the magnetic material should the magnetic material remain exposed during the wet chemistry processes. The patterned sealant is removed subsequent to the semiconductor package processing steps involving wet chemistry.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Chong Zhang, Yikang Deng, Junnan Zhao, Ying Wang
  • Patent number: 10777514
    Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Yikang Deng, Kyu Oh Lee, Ji Yong Park, Srinivas Pietambaram, Ying Wang, Chong Zhang, Rui Zhang, Junnan Zhao
  • Publication number: 20200273776
    Abstract: An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Cheng Xu, Junnan Zhao, Zhimin Wan, Ying Wang, Yikang Deng, Chong Zhang, Jiwei Sun, Zhenguo Jiang, Kyu-Oh Lee
  • Publication number: 20200211927
    Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.
    Type: Application
    Filed: December 27, 2018
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Zhimin Wan, Cheng Xu, Yikang Deng, Junnan Zhao, Ying Wang, Chong Zhang, Kyu Oh Lee, Chandra Mohan Jha, Chia-Pin Chiu
  • Publication number: 20200185300
    Abstract: An integrated circuit (IC) package comprises a substrate comprising a dielectric and a thermal conduit that is embedded within the dielectric. The thermal conduit has a length that extends laterally within the dielectric from a first end to a second end. An IC die is thermally coupled to the first end of the thermal conduit. The IC die comprises an interconnect that is coupled to the first end of the thermal conduit. An integrated heat spreader comprises a lid over the IC die and at least one sidewall extending from the edge of the lid to the substrate that is thermally coupled to the second end of the thermal conduit.
    Type: Application
    Filed: December 10, 2018
    Publication date: June 11, 2020
    Applicant: INTEL CORPORATION
    Inventors: Cheng Xu, Zhimin Wan, Lingtao Liu, Yikang Deng, Junnan Zhao, Chandra Mohan Jha, Kyu-oh Lee
  • Publication number: 20200185289
    Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 27, 2016
    Publication date: June 11, 2020
    Applicant: Intel Corporation
    Inventors: Mitul MODI, Robert L. SANKMAN, Debendra MALLIK, Ravindranath V. MAHAJAN, Amruthavalli P. ALUR, Yikang DENG, Eric J. LI
  • Publication number: 20200168384
    Abstract: Described herein are magnetic core inductors (MCI) and methods for manufacturing magnetic core inductors. A first embodiment of the MCI can be a snake-configuration MCI. The snake-configuration MCI can be formed by creating an opening in a base material, such as copper, and providing a nonconductive magnetic material in the opening. The inductor can be further formed by forming plated through holes into the core material. The conductive elements for the inductor can be formed in the plated through holes. The nonconductive magnetic material surrounds each conductive element and plated through hole. In embodiments, a layered coil inductor can be formed by drilling a laminate to form a cavity through the laminate within the metal rings of the layered coil inductor. The nonconductive magnetic material can be provided in the cavity.
    Type: Application
    Filed: September 28, 2017
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Junnan Zhao, Ying Wang, Cheng Xu, Kyu Oh Lee, Sheng Li, Yikang Deng