Abstract: A metal protected fan-out cavity enables assembly of a package-on-package (PoP) integrated circuit while reducing PoP solder spacing and overall z-height. A horizontal fan-out conductor provides a contact between a die contact and a lower package via. A metal protection layer may be used during manufacture to protect the fan-out conductor, such as providing a laser stop during laser skiving. The metal protection layer materials and an etching solution may be selected to allow for subsequent removal via etching while leaving the fan-out conductor intact. The metal protection layer and fan-out conductor materials may also be selected to reduce or eliminate formation of an intermetallic compound (IMC) between the metal protection layer and the fan-out conductor.

Abstract: A microelectronic substrate may be formed to have an embedded trace which includes an integral attachment structure that extends beyond a first surface of a dielectric layer of the microelectronic substrate for the attachment of a microelectronic device. In one embodiment, the embedded trace may be fabricated by forming a dummy layer, forming a recess in the dummy layer, conformally depositing surface finish in the recess, forming an embedded trace layer on the dummy layer and abutting the surface finish, and removing the dummy layer.

Abstract: Integrated circuit (IC) package structures, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include: a dielectric layer having a first face and a second face; a metal layer disposed at the first face of the dielectric layer and having a first face and a second face, wherein the second face of the metal layer is disposed between the first face of the metal layer and the second face of the dielectric layer; a package contact at the first face of the metal layer to couple the IC package substrate to a component; and a die contact at the first face of the metal layer to couple a die to the IC package substrate.

Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.

Abstract: Integrated circuit (IC) package structures, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include: a dielectric layer having a first face and a second face; a metal layer disposed at the first face of the dielectric layer and having a first face and a second face, wherein the second face of the metal layer is disposed between the first face of the metal layer and the second face of the dielectric layer; a package contact at the first face of the metal layer to couple the IC package substrate to a component; and a die contact at the first face of the metal layer to couple a die to the IC package substrate.

Abstract: A microelectronic substrate may be formed to have an embedded trace which includes an integral attachment structure that extends beyond a first surface of a dielectric layer of the microelectronic substrate for the attachment of a microelectronic device. In one embodiment, the embedded trace may be fabricated by forming a dummy layer, forming a recess in the dummy layer, conformally depositing surface finish in the recess, forming an embedded trace layer on the dummy layer and abutting the surface finish, and removing the dummy layer.

Abstract: A microelectronic substrate may be formed to have an embedded trace which includes an integral attachment structure that extends beyond a first surface of a dielectric layer of the microelectronic substrate for the attachment of a microelectronic device. In one embodiment, the embedded trace may be fabricated by forming a dummy layer, forming a recess in the dummy layer, conformally depositing surface finish in the recess, forming an embedded trace layer on the dummy layer and abutting the surface finish, and removing the dummy layer.

Abstract: A microelectronic substrate having a substrate core with at least one plated through hole extending therethrough, wherein the plated through hole includes a fluorescent conductive fill material. In one embodiment, the plated through hole may comprise a hole defined to extend from a first surface to an opposing second surface of the substrate core, wherein a conductive material layer is formed on a sidewall(s) of the substrate core hole and a conductive fill material, having a fluorescent component, is disposed to fill the remaining substrate core hole after forming the conductive material layer. In another embodiment of the present description, the fluorescent conductive fill material is used for the detection of defects.

Abstract: A microelectronic substrate having a substrate core with at least one plated through hole extending therethrough, wherein the plated through hole includes a fluorescent conductive fill material. In one embodiment, the plated through hole may comprise a hole defined to extend from a first surface to an opposing second surface of the substrate core, wherein a conductive material layer is formed on a sidewall(s) of the substrate core hole and a conductive fill material, having a fluorescent component, is disposed to fill the remaining substrate core hole after forming the conductive material layer. In another embodiment of the present description, the fluorescent conductive fill material is used for the detection of defects.

Abstract: In one aspect, the present disclosure relates to a method of processing a thin film including, while advancing a thin film in a first selected direction, irradiating a first region of the thin film with a first laser pulse and a second laser pulse, each laser pulse providing a shaped beam and having a fluence that is sufficient to partially melt the thin film and the first region re-solidifying and crystallizing to form a first crystallized region, and irradiating a second region of the thin film with a third laser pulse and a fourth laser pulse, each pulse providing a shaped beam and having a fluence that is sufficient to partially melt the thin film and the second region re-solidifying and crystallizing to form a second crystallized region, wherein the time interval between the first laser pulse and the second laser pulse is less than half the time interval between the first laser pulse and the third laser pulse.

Abstract: In one aspect, the present disclosure relates to a method of processing a thin film including, while advancing a thin film in a first selected direction, irradiating a first region of the thin film with a first laser pulse and a second laser pulse, each laser pulse providing a shaped beam and having a fluence that is sufficient to partially melt the thin film and the first region re-solidifying and crystallizing to form a first crystallized region, and irradiating a second region of the thin film with a third laser pulse and a fourth laser pulse, each pulse providing a shaped beam and having a fluence that is sufficient to partially melt the thin film and the second region re-solidifying and crystallizing to form a second crystallized region, wherein the time interval between the first laser pulse and the second laser pulse is less than half the time interval between the first laser pulse and the third laser pulse.