Patents by Inventor Yikang Deng
Yikang Deng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220310512Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.Type: ApplicationFiled: June 13, 2022Publication date: September 29, 2022Applicant: INTEL CORPORATIONInventors: Huong Do, Kaladhar Radhakrishnan, Krishna Bharath, Yikang Deng, Amruthavalli P. Alur
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Patent number: 11444042Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line and a magnetic structure around a top surface of the conductive line and side surfaces of the conductive line. The magnetic structure may have a tapered shape that narrows toward the conductive line.Type: GrantFiled: June 5, 2018Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Andrew James Brown, Ying Wang, Chong Zhang, Lauren Ashley Link, Yikang Deng
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Publication number: 20220278038Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.Type: ApplicationFiled: May 12, 2022Publication date: September 1, 2022Applicant: Intel CorporationInventors: Ji Yong Park, Kyu Oh Lee, Yikang Deng, Zhichao Zhang, Liwei Cheng, Andrew James Brown, Cheng Xu, Jiwei Sun
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Patent number: 11404364Abstract: A microelectronics package comprises a substrate that comprises a dielectric and at least two conductor layers within the dielectric, and an inductor structure having a magnetic core at least partially within the dielectric and extending at least between a first conductor layer and a second conductor layer. The inductor structure comprises at least one conductor that extends horizontally at least partially within the magnetic core. The conductor extends in the z-direction within the magnetic core between the first conductor layer and the second conductor layer. One or more vias extend within the dielectric adjacent to the magnetic core between the first conductor layer and the second conductor layer. The conductor of the inductor has a length extending through the magnetic core that is greater than a width of the conductor.Type: GrantFiled: August 22, 2018Date of Patent: August 2, 2022Assignee: Intel CorporationInventors: Huong Do, Kaladhar Radhakrishnan, Krishna Bharath, Yikang Deng, Amruthavalli P. Alur
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Publication number: 20220238402Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: April 13, 2022Publication date: July 28, 2022Applicant: Intel CorporationInventors: Mitul MODI, Robert L. SANKMAN, Debendra MALLIK, Ravindranath V. MAHAJAN, Amruthavalli P. ALUR, Yikang DENG, Eric J. LI
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Publication number: 20220230800Abstract: Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.Type: ApplicationFiled: April 5, 2022Publication date: July 21, 2022Inventors: Cheng Xu, Yikang Deng, Kyu Oh Lee, Ji Yong Park, Srinivas Venkata Ramanuja Pietambaram, Ying Wang, Chong Zhang, Rui Zhang, Junnan Zhao
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Patent number: 11393751Abstract: A microelectronics package comprising a substrate, the substrate comprising a dielectric and at least first and second conductor level within the dielectric, where the first and second conductor levels are separated by at least one dielectric layer. The microelectronics package comprises an inductor structure that comprises a magnetic core. The magnetic core is at least partially embedded within the dielectric. The inductor structure comprises a first trace in the first conductor level, a second trace in the second conductor level, and a via interconnect connecting the first and second traces. The first trace and the second trace extend at least partially within the magnetic core.Type: GrantFiled: August 21, 2018Date of Patent: July 19, 2022Assignee: Intel CorporationInventors: Huong Do, Kaladhar Radhakrishnan, Krishna Bharath, Yikang Deng, Amruthavalli P. Alur
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Patent number: 11387224Abstract: A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a cavity, and phase change material within the cavity. In an example, the phase change material has a phase change temperature lower than 120 degree centigrade. A die may be coupled to the substrate. In an example, the semiconductor device package structure includes one or more interconnect structures that are to couple the die to the phase change material within the cavity.Type: GrantFiled: October 11, 2018Date of Patent: July 12, 2022Assignee: Intel CorporationInventors: Cheng Xu, Zhimin Wan, Yikang Deng, Junnan Zhao, Chong Zhang, Chandra Mohan M Jha, Ying Wang, Kyu-oh Lee
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Patent number: 11380609Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.Type: GrantFiled: May 21, 2018Date of Patent: July 5, 2022Assignee: Intel CorporationInventors: Cheng Xu, Jiwei Sun, Ji Yong Park, Kyu Oh Lee, Yikang Deng, Zhichao Zhang, Liwei Cheng, Andrew James Brown
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Publication number: 20220183157Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.Type: ApplicationFiled: February 22, 2022Publication date: June 9, 2022Applicant: INTEL CORPORATIONInventors: Kristof Darmawikarta, Robert A. May, Yikang Deng, Ji Yong Park, Maroun D. Moussallem, Amruthavalli P. Alur, Sri Ranga Sai Boyapati, Lilia May
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Patent number: 11328968Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 27, 2016Date of Patent: May 10, 2022Assignee: Intel CorporationInventors: Mitul Modi, Robert L. Sankman, Debendra Mallik, Ravindranath V. Mahajan, Amruthavalli P. Alur, Yikang Deng, Eric J. Li
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Patent number: 11322290Abstract: Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.Type: GrantFiled: June 19, 2018Date of Patent: May 3, 2022Assignee: Intel CorporationInventors: Cheng Xu, Yikang Deng, Kyu Oh Lee, Ji Yong Park, Srinivas Pietambaram, Ying Wang, Chong Zhang, Rui Zhang, Junnan Zhao
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Publication number: 20220117089Abstract: Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.Type: ApplicationFiled: December 22, 2021Publication date: April 14, 2022Inventors: Chong ZHANG, Ying WANG, Junnan ZHAO, Cheng XU, Yikang DENG
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Patent number: 11272619Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.Type: GrantFiled: September 2, 2016Date of Patent: March 8, 2022Assignee: Intel CorporationInventors: Kristof Darmawikarta, Robert A. May, Yikang Deng, Ji Yong Park, Maroun D. Moussallem, Amruthavalli P. Alur, Sri Ranga Sai Boyapati, Lilia May
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Patent number: 11246218Abstract: Embodiments may include inductors with embedded magnetic cores and methods of making such inductors. In an embodiment, an integrated circuit package may include an integrated circuit die with a multi-phase voltage regulator electrically coupled to the integrated circuit die. In such embodiments, the multi-phase voltage regulator may include a substrate core and a plurality of inductors. The inductors may include a conductive through-hole disposed through the substrate core and a plugging layer comprising a dielectric material surrounding the conductive through-hole. In an embodiment, a magnetic sheath is formed around the plugging layer. In an embodiment, the magnetic sheath is separated from the plated through hole by the plugging layer. Additionally, a first layer comprising a dielectric material may be disposed over a first surface of the magnetic sheath, and a second layer comprising a dielectric material may be disposed over a second surface of the magnetic sheath.Type: GrantFiled: March 2, 2018Date of Patent: February 8, 2022Assignee: Intel CorporationInventors: Chong Zhang, Ying Wang, Junnan Zhao, Cheng Xu, Yikang Deng
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Publication number: 20210391263Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.Type: ApplicationFiled: June 16, 2020Publication date: December 16, 2021Applicant: Intel CorporationInventors: Bai Nie, Gang Duan, Omkar G. Karhade, Nitin A. Deshpande, Yikang Deng, Wei-Lun Jen, Tarek A. Ibrahim, Sri Ranga Sai Boyapati, Robert Alan May, Yosuke Kanaoka, Robin Shea McRee, Rahul N. Manepalli
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Publication number: 20210304952Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.Type: ApplicationFiled: March 26, 2021Publication date: September 30, 2021Inventors: William J. Lambert, Mihir K. Roy, Mathew J. Manusharow, Yikang Deng
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Publication number: 20210305154Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line, a magnetic structure around the conductive line, and material stubs at side faces of the magnetic structure.Type: ApplicationFiled: March 25, 2020Publication date: September 30, 2021Applicant: Intel CorporationInventors: Ying Wang, Yikang Deng, Junnan Zhao, Andrew James Brown, Cheng Xu, Kaladhar Radhakrishnan
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Publication number: 20210307172Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.Type: ApplicationFiled: September 2, 2016Publication date: September 30, 2021Applicant: INTEL CORPORATIONInventors: Kristof Darmawikarta, Robert A. May, Yikang Deng, Ji Yong Park, Maroun D. Moussallem, Amruthavalli P. Alur, Sri Ranga Sai Boyapati, Lilia May
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Publication number: 20210273036Abstract: An integrated circuit (IC) package substrate, comprising a magnetic material embedded within a dielectric material. A first surface of the dielectric material is below the magnetic material, and a second surface of the dielectric material, opposite the first surface, is over the magnetic material. A metallization level comprising a first metal feature is embedded within the magnetic material. A second metal feature is at an interface of the magnetic material and the dielectric material. The second metal feature has a first sidewall in contact with the dielectric material and a second sidewall in contact with the magnetic material.Type: ApplicationFiled: February 28, 2020Publication date: September 2, 2021Applicant: Intel CorporationInventors: Brandon C. Marin, Tarek Ibrahim, Prithwish Chatterjee, Haifa Hariri, Yikang Deng, Sheng C. Li, Srinivas Pietambaram