Patents by Inventor Yimin Huang

Yimin Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240371900
    Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate. A grid structure extends from a first side of the semiconductor substrate to within the semiconductor substrate. An image sensing element is disposed within the semiconductor substrate and is laterally surrounded by the grid structure. A plurality of protrusions are arranged along the first side of the semiconductor substrate. The plurality of protrusions are disposed over the image sensing element and are laterally surrounded by the grid structure. The plurality of protrusions are substantially identical to one another and have a characteristic dimension. An inner surface of the grid structure facing the image sensing element is spaced apart from a point of one of the plurality of protrusions by a predetermined reflective length that is based on the characteristic dimension of the plurality of protrusions.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Chin-Chia Kuo, Jhy-Jyi Sze, Tung-Ting Wu, Yimin Huang
  • Patent number: 12136638
    Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate. A grid structure extends from a first side of the semiconductor substrate to within the semiconductor substrate. An image sensing element is disposed within the semiconductor substrate and is laterally surrounded by the grid structure. A plurality of protrusions are arranged along the first side of the semiconductor substrate. The plurality of protrusions are disposed over the image sensing element and are laterally surrounded by the grid structure. The plurality of protrusions are substantially identical to one another and have a characteristic dimension. An inner surface of the grid structure facing the image sensing element is spaced apart from a point of one of the plurality of protrusions by a predetermined reflective length that is based on the characteristic dimension of the plurality of protrusions.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: November 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chia Kuo, Jhy-Jyi Sze, Tung-Ting Wu, Yimin Huang
  • Publication number: 20240355764
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a plurality of semiconductor devices arranged on a substrate and within a device region. A first isolation structure is arranged in the device region and laterally between adjacent semiconductor devices in the plurality of semiconductor devices. An interconnect structure underlies the substrate and includes a topmost conductive interconnect element adjacent to the substrate. A second isolation structure is disposed in the substrate and around the device region. A bottom surface of the second isolation structure is above a lower surface of the topmost conductive interconnect element.
    Type: Application
    Filed: July 3, 2024
    Publication date: October 24, 2024
    Inventors: Tung-Ting Wu, Chen-Jong Wang, Jen-Cheng Liu, Yimin Huang, Chin-Chia Kuo
  • Publication number: 20240355978
    Abstract: A circuit board includes a substrate and a stress neutral layer disposed on a side of the substrate. The stress neutral layer includes one or more first metal layers and one or more second metal layers. The one or more second metal layers and the one or more first metal layers are stacked. At least one of the one or more first metal layers is made of a material for generating a tensile stress, and at least one of the one or more second metal layers is made of a material for generating a compressive stress.
    Type: Application
    Filed: April 21, 2022
    Publication date: October 24, 2024
    Inventors: Nianqi YAO, Zhongpeng TIAN, Ce NING, Zhengliang LI, Hehe HU, Jie HUANG, Jiayu HE, Feifei LI, Kun ZHAO, Yimin CHEN
  • Publication number: 20240347999
    Abstract: A multiple frequency laser system and method for treating skin conditions via a handpiece features a pump laser module having a single laser beam at a first frequency. A dual laser module receives the laser beam at the first frequency and includes dual free running laser resonators to produce a laser beam at a second frequency and a laser beam at a third frequency. A frequency conversion module receives as inputs the laser beam at the second frequency and the laser beam at the third frequency and is configured to selectively provide laser beams to the handpiece including a second harmonic generation of the second frequency, a second harmonic generation of the third frequency, a summed frequency generation of the second frequency and the third frequency, the laser beam at the first frequency, the laser beam at the second frequency, and/or the laser beam at the first frequency combined with the laser beam at the second frequency.
    Type: Application
    Filed: April 5, 2024
    Publication date: October 17, 2024
    Inventors: Xiaoming Shang, Zhi Huang, Yimin Zang, Kevin Schomacker
  • Patent number: 12110291
    Abstract: The present disclosure relates to novel pan-KRAS glutarimide-containing compounds with KRAS degradation activities, pharmaceutical compositions containing such compounds, and their use in prevention and treatment diseases and conditions.
    Type: Grant
    Filed: November 30, 2023
    Date of Patent: October 8, 2024
    Assignee: Tiger Biotherapeutics Inc.
    Inventors: Robert Luo, Ji Liu, Pin Huang, Jie Su, Yan Feng, Ke Liu, Jie Fan, Wei He, Yimin Qian
  • Publication number: 20240332338
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a masking layer on a first side of a substrate. A first etching process is performed on the first side of the substrate with the masking layer in place. The masking layer is removed. A second wet etching process is performed on the first side of the substrate after removing the masking layer. The first etching process and the second wet etching process collectively form a plurality of topographical features respectively having a triangular shape in a cross-section.
    Type: Application
    Filed: June 12, 2024
    Publication date: October 3, 2024
    Inventors: Tung-Ting Wu, Jhy-Jyi Sze, Yimin Huang
  • Publication number: 20240334583
    Abstract: An automatic X-ray exposure control method and system are disclosed. The method comprises: turning on a flat-panel detector, setting parameters of the flat-panel detector, and selecting one or more exposure radiation fields of the flat-panel detector; testing a corresponding exposure dose obtained by scanning the exposure radiation fields in real time, and determining that an exposure has started when the tested exposure dose is greater than a first preset threshold; configuring the flat-panel detector such that it enters an automatic exposure control mode when the exposure is started and triggers a cut-off signal; configuring the flat-panel detector such that it triggers an image acquisition when the exposure is completed. The present disclosed method and system can simplify the structure, reduce the cost, and effectively avoid exposure dose errors caused by line delays and other problems. Meanwhile, it also shortens the image acquisition cycle and reduces the complexity of operation.
    Type: Application
    Filed: July 8, 2021
    Publication date: October 3, 2024
    Applicant: IRAY TECHNOLOGY COMPANY LIMITED
    Inventors: YIMIN HUANG, CHENGLIN HE
  • Patent number: 12100726
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate. One or more isolation structures are arranged within one or more trenches in the semiconductor substrate. The one or more trenches are disposed along opposing sides of a photo diode region within the semiconductor substrate. The semiconductor substrate includes an undulating exterior having rounded corners arranged laterally between neighboring ones of a plurality of flat surfaces. The rounded corners and the plurality of flat surfaces forming a plurality of triangular shaped protrusions arranged between the one or more isolation structures, as viewed along a cross-sectional view.
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: September 24, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ting Wu, Jhy-Jyi Sze, Yimin Huang
  • Publication number: 20240313010
    Abstract: In some embodiments, the present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a floating diffusion node disposed within a substrate. A plurality of photodetectors are disposed around the floating diffusion node, as viewed in a plan-view, and a plurality of transfer transistor gates are disposed between the floating diffusion node and the plurality of photodetectors, as viewed in the plan-view. One or more transistor gates are disposed on the substrate. A device isolation structure extends in a closed loop around the one or more transistor gates. The device isolation structure is laterally offset from the floating diffusion node.
    Type: Application
    Filed: May 31, 2024
    Publication date: September 19, 2024
    Inventors: Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Feng-Chi Hung, Feng-Jia Shiu, Jen-Cheng Liu, Jhy-Jyi Sze, Chun-Wei Chang, Wei-Cheng Hsu, Wei Chuang Wu, Yimin Huang
  • Publication number: 20240294611
    Abstract: Provided herein are antibodies and antibody fragments that bind to the S2 domains of SARS-CoV-2, SARS-CoV, and MERS-CoV spike proteins. Methods of using these antibodies in in vitro methods are provided. Methods of using these antibodies in vivo to treat or prevent SARS-CoV-2 infections are also provided.
    Type: Application
    Filed: January 11, 2022
    Publication date: September 5, 2024
    Inventors: Jennifer MAYNARD, Yimin HUANG, Annalee NGUYEN, Ching-Lin HSIEH, Jason MCLELLAN, Rui P. SILVA, Edurado PADLAN
  • Publication number: 20240294527
    Abstract: The present disclosure relates to novel pan-KRAS glutarimide-containing compounds with KRAS degradation activities, pharmaceutical compositions containing such compounds, and their use in prevention and treatment diseases and conditions.
    Type: Application
    Filed: April 24, 2024
    Publication date: September 5, 2024
    Inventors: Robert LUO, Ji LIU, Pin HUANG, Jie SU, Yan FENG, Ke LIU, Jie FAN, Wei HE, Yimin QIAN
  • Patent number: 12057412
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor device, the method including forming a plurality of photodetectors in a substrate. A device isolation structure is formed within the substrate. The device isolation structure laterally wraps around the plurality of photodetectors. An outer isolation structure is formed within the substrate. The device isolation structure is spaced between sidewalls of the outer isolation structure. The device isolation structure and the outer isolation structure comprise a dielectric material.
    Type: Grant
    Filed: April 21, 2022
    Date of Patent: August 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ting Wu, Chen-Jong Wang, Jen-Cheng Liu, Yimin Huang, Chin-Chia Kuo
  • Patent number: 12044180
    Abstract: An igniter for a combustor of a turbomachine includes a fuel inlet in fluid communication with a mixing plenum. The mixing plenum is positioned upstream of a mixing channel. An air inlet is in fluid communication with the mixing plenum and an ignition source is in operative communication with the mixing channel. The igniter may include a mounting flange configured for coupling the igniter to the combustor. The ignition source may be positioned proximate to a downstream end of the mixing channel and upstream of the mounting flange. The mixing channel may define a venturi shape. The venturi shape includes a converging section between an upstream end of the mixing channel and a venturi throat.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: July 23, 2024
    Assignee: GE Infrastructure Technology LLC
    Inventors: Lucas John Stoia, Yimin Huang, Abdul Khan, Thomas Edward Johnson, Heath M. Ostebee, Jayaprakash Natarajan
  • Patent number: 12040336
    Abstract: In some embodiments, the present disclosure relates to method for forming an image sensor integrated chip. The method includes forming a first photodetector region in a substrate and forming a second photodetector region in the substrate. A floating diffusion node is formed in the substrate between the first photodetector region and the second photodetector region. A pick-up well contact region is formed in the substrate. A first line intersects the floating diffusion node and the pick-up well contact region. One or more transistor gates are formed on the substrate. A second line that is perpendicular to the first line intersects the pick-up well contact region and the one or more transistor gates.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Seiji Takahashi, Chen-Jong Wang, Dun-Nian Yaung, Feng-Chi Hung, Feng-Jia Shiu, Jen-Cheng Liu, Jhy-Jyi Sze, Chun-Wei Chang, Wei-Cheng Hsu, Wei Chuang Wu, Yimin Huang
  • Patent number: 12029832
    Abstract: A cardiac patch for treatment of a mammalian heart including perfusable vessels embedded integratedly between two layers of anisotropically oriented myocardial fibers. The cardiac patch is made using a dual 3D bioprinting technique using stereolithography to form an anisotropic construct and extrusion printing to form perfusion vessels. A nutrient and oxygen containing media can be provided within the perfusion vessels for growth of cells in the cardiac patch. The technique permits larger patches to be made for the treatment of cardiac damage in both small and large mammalian hearts.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: July 9, 2024
    Assignee: The George Washington University
    Inventors: Haitao Cui, Lijie Grace Zhang, Yimin Huang
  • Patent number: 11955547
    Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Patent number: 11811457
    Abstract: A method for generating millimeter wave noise with a flat RF (radio frequency) spectrum includes the following steps. A noise optical signal with an optical spectrum in Gaussian shape is output by a first optical emission module. The noise optical signal is transmitted to an optical coupler. n beams of noise optical signals with optical spectra in Gaussian shape is output by a second optical emission module. The noise optical signals is transmitted to the optical coupler. The noise light generated by the first optical emission module and the second optical emission module is coupled to the optical coupler. The coupled optical signals is transmitted to a photodetector. The beat frequency is performed by the photodetector to realize mapping transformation from the optical spectra to the RF spectra. The flat millimeter wave noise is output.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: November 7, 2023
    Assignee: GUANGDONG UNIVERSITY OF TECHNOLOGY
    Inventors: Yuncai Wang, Yimin Huang, Yuehui Sun, Wenjie Liu, Zhensen Gao, Yu Cheng
  • Publication number: 20230261753
    Abstract: A method for generating millimeter wave noise with a flat RF (radio frequency) spectrum includes the following steps. A noise optical signal with an optical spectrum in Gaussian shape is output by a first optical emission module. The noise optical signal is transmitted to an optical coupler. n beams of noise optical signals with optical spectra in Gaussian shape is output by a second optical emission module. The noise optical signals is transmitted to the optical coupler. The noise light generated by the first optical emission module and the second optical emission module is coupled to the optical coupler. The coupled optical signals is transmitted to a photodetector. The beat frequency is performed by the photodetector to realize mapping transformation from the optical spectra to the RF spectra. The flat millimeter wave noise is output.
    Type: Application
    Filed: July 21, 2021
    Publication date: August 17, 2023
    Applicant: GUANGDONG UNIVERSITY OF TECHNOLOGY
    Inventors: Yuncai WANG, Yimin HUANG, Yuehui SUN, Wenjie LIU, Zhensen GAO, Yu CHENG
  • Publication number: 20230253434
    Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate. One or more isolation structures are arranged within one or more trenches in the semiconductor substrate. The one or more trenches are disposed along opposing sides of a photo-diode region within the semiconductor substrate. The semiconductor substrate includes an undulating exterior having rounded corners arranged laterally between neighboring ones of a plurality of flat surfaces. The rounded corners and the plurality of flat surfaces forming a plurality of triangular shaped protrusions arranged between the one or more isolation structures, as viewed along a cross-sectional view.
    Type: Application
    Filed: April 21, 2023
    Publication date: August 10, 2023
    Inventors: Tung-Ting Wu, Jhy-Jyi Sze, Yimin Huang