Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate. A grid structure extends from a first side of the semiconductor substrate to within the semiconductor substrate. An image sensing element is disposed within the semiconductor substrate and is laterally surrounded by the grid structure. A plurality of protrusions are arranged along the first side of the semiconductor substrate. The plurality of protrusions are disposed over the image sensing element and are laterally surrounded by the grid structure. The plurality of protrusions are substantially identical to one another and have a characteristic dimension. An inner surface of the grid structure facing the image sensing element is spaced apart from a point of one of the plurality of protrusions by a predetermined reflective length that is based on the characteristic dimension of the plurality of protrusions.

Abstract: The present disclosure relates to a semiconductor device including a semiconductor substrate. A grid structure extends from a first side of the semiconductor substrate to within the semiconductor substrate. An image sensing element is disposed within the semiconductor substrate and is laterally surrounded by the grid structure. A plurality of protrusions are arranged along the first side of the semiconductor substrate. The plurality of protrusions are disposed over the image sensing element and are laterally surrounded by the grid structure. The plurality of protrusions are substantially identical to one another and have a characteristic dimension. An inner surface of the grid structure facing the image sensing element is spaced apart from a point of one of the plurality of protrusions by a predetermined reflective length that is based on the characteristic dimension of the plurality of protrusions.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a plurality of semiconductor devices arranged on a substrate and within a device region. A first isolation structure is arranged in the device region and laterally between adjacent semiconductor devices in the plurality of semiconductor devices. An interconnect structure underlies the substrate and includes a topmost conductive interconnect element adjacent to the substrate. A second isolation structure is disposed in the substrate and around the device region. A bottom surface of the second isolation structure is above a lower surface of the topmost conductive interconnect element.

Abstract: An automatic X-ray exposure control method and system are disclosed. The method comprises: turning on a flat-panel detector, setting parameters of the flat-panel detector, and selecting one or more exposure radiation fields of the flat-panel detector; testing a corresponding exposure dose obtained by scanning the exposure radiation fields in real time, and determining that an exposure has started when the tested exposure dose is greater than a first preset threshold; configuring the flat-panel detector such that it enters an automatic exposure control mode when the exposure is started and triggers a cut-off signal; configuring the flat-panel detector such that it triggers an image acquisition when the exposure is completed. The present disclosed method and system can simplify the structure, reduce the cost, and effectively avoid exposure dose errors caused by line delays and other problems. Meanwhile, it also shortens the image acquisition cycle and reduces the complexity of operation.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a masking layer on a first side of a substrate. A first etching process is performed on the first side of the substrate with the masking layer in place. The masking layer is removed. A second wet etching process is performed on the first side of the substrate after removing the masking layer. The first etching process and the second wet etching process collectively form a plurality of topographical features respectively having a triangular shape in a cross-section.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate. One or more isolation structures are arranged within one or more trenches in the semiconductor substrate. The one or more trenches are disposed along opposing sides of a photo diode region within the semiconductor substrate. The semiconductor substrate includes an undulating exterior having rounded corners arranged laterally between neighboring ones of a plurality of flat surfaces. The rounded corners and the plurality of flat surfaces forming a plurality of triangular shaped protrusions arranged between the one or more isolation structures, as viewed along a cross-sectional view.

Abstract: In some embodiments, the present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a floating diffusion node disposed within a substrate. A plurality of photodetectors are disposed around the floating diffusion node, as viewed in a plan-view, and a plurality of transfer transistor gates are disposed between the floating diffusion node and the plurality of photodetectors, as viewed in the plan-view. One or more transistor gates are disposed on the substrate. A device isolation structure extends in a closed loop around the one or more transistor gates. The device isolation structure is laterally offset from the floating diffusion node.

Abstract: Provided herein are antibodies and antibody fragments that bind to the S2 domains of SARS-CoV-2, SARS-CoV, and MERS-CoV spike proteins. Methods of using these antibodies in in vitro methods are provided. Methods of using these antibodies in vivo to treat or prevent SARS-CoV-2 infections are also provided.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor device, the method including forming a plurality of photodetectors in a substrate. A device isolation structure is formed within the substrate. The device isolation structure laterally wraps around the plurality of photodetectors. An outer isolation structure is formed within the substrate. The device isolation structure is spaced between sidewalls of the outer isolation structure. The device isolation structure and the outer isolation structure comprise a dielectric material.

Abstract: An igniter for a combustor of a turbomachine includes a fuel inlet in fluid communication with a mixing plenum. The mixing plenum is positioned upstream of a mixing channel. An air inlet is in fluid communication with the mixing plenum and an ignition source is in operative communication with the mixing channel. The igniter may include a mounting flange configured for coupling the igniter to the combustor. The ignition source may be positioned proximate to a downstream end of the mixing channel and upstream of the mounting flange. The mixing channel may define a venturi shape. The venturi shape includes a converging section between an upstream end of the mixing channel and a venturi throat.

Abstract: In some embodiments, the present disclosure relates to method for forming an image sensor integrated chip. The method includes forming a first photodetector region in a substrate and forming a second photodetector region in the substrate. A floating diffusion node is formed in the substrate between the first photodetector region and the second photodetector region. A pick-up well contact region is formed in the substrate. A first line intersects the floating diffusion node and the pick-up well contact region. One or more transistor gates are formed on the substrate. A second line that is perpendicular to the first line intersects the pick-up well contact region and the one or more transistor gates.

Abstract: A cardiac patch for treatment of a mammalian heart including perfusable vessels embedded integratedly between two layers of anisotropically oriented myocardial fibers. The cardiac patch is made using a dual 3D bioprinting technique using stereolithography to form an anisotropic construct and extrusion printing to form perfusion vessels. A nutrient and oxygen containing media can be provided within the perfusion vessels for growth of cells in the cardiac patch. The technique permits larger patches to be made for the treatment of cardiac damage in both small and large mammalian hearts.

Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

Abstract: A method for generating millimeter wave noise with a flat RF (radio frequency) spectrum includes the following steps. A noise optical signal with an optical spectrum in Gaussian shape is output by a first optical emission module. The noise optical signal is transmitted to an optical coupler. n beams of noise optical signals with optical spectra in Gaussian shape is output by a second optical emission module. The noise optical signals is transmitted to the optical coupler. The noise light generated by the first optical emission module and the second optical emission module is coupled to the optical coupler. The coupled optical signals is transmitted to a photodetector. The beat frequency is performed by the photodetector to realize mapping transformation from the optical spectra to the RF spectra. The flat millimeter wave noise is output.

Abstract: A method for generating millimeter wave noise with a flat RF (radio frequency) spectrum includes the following steps. A noise optical signal with an optical spectrum in Gaussian shape is output by a first optical emission module. The noise optical signal is transmitted to an optical coupler. n beams of noise optical signals with optical spectra in Gaussian shape is output by a second optical emission module. The noise optical signals is transmitted to the optical coupler. The noise light generated by the first optical emission module and the second optical emission module is coupled to the optical coupler. The coupled optical signals is transmitted to a photodetector. The beat frequency is performed by the photodetector to realize mapping transformation from the optical spectra to the RF spectra. The flat millimeter wave noise is output.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate. One or more isolation structures are arranged within one or more trenches in the semiconductor substrate. The one or more trenches are disposed along opposing sides of a photo-diode region within the semiconductor substrate. The semiconductor substrate includes an undulating exterior having rounded corners arranged laterally between neighboring ones of a plurality of flat surfaces. The rounded corners and the plurality of flat surfaces forming a plurality of triangular shaped protrusions arranged between the one or more isolation structures, as viewed along a cross-sectional view.

Abstract: The problem of reducing noise in image sensing devices, especially NIR detectors, is solved by providing ground connections for the reflectors. The reflectors may be grounded through vias that couple the reflectors to grounded areas of the substrate. The grounded areas of the substrate may be P+ doped areas formed proximate the surface of the substrate. In particular, the P+ doped areas may be parts of photodiodes. Alternatively, the reflectors may be grounded through a metal interconnect structure formed over the front side of the substrate.

Abstract: In some embodiments, the present disclosure relates to an image sensor, including a first photodiode and a second photodiode disposed in a semiconductor substrate. A floating diffusion node is disposed along a frontside of the semiconductor substrate and between the first and second photodiodes. A partial backside deep trench isolation (BDTI) structure is disposed within the semiconductor substrate and between the first and second photodiodes. The partial BDTI extends from a backside of the semiconductor substrate and is spaced from the floating diffusion node. A full BDTI structure extends from the backside of the semiconductor substrate to the frontside of the semiconductor substrate.

Abstract: The present disclosure, in some embodiments, relates to an image sensing integrated chip. The image sensing integrated chip includes a semiconductor substrate having sidewalls defining one or more trenches on opposing sides of a region of the semiconductor substrate. One or more dielectrics are disposed within the one or more trenches. The semiconductor substrate has a plurality of flat surfaces arranged between the one or more trenches. Adjacent ones of the plurality of flat surfaces define a plurality of triangular shaped protrusions and alternative ones of the plurality of flat surfaces are substantially parallel to one another, as viewed along a cross-sectional view.

Abstract: In some embodiments, the present disclosure relates to method for forming an image sensor integrated chip. The method includes forming a first photodetector region in a substrate and forming a second photodetector region in the substrate. A floating diffusion node is formed in the substrate between the first photodetector region and the second photodetector region. A pick-up well contact region is formed in the substrate. A first line intersects the floating diffusion node and the pick-up well contact region. One or more transistor gates are formed on the substrate. A second line that is perpendicular to the first line intersects the pick-up well contact region and the one or more transistor gates.