Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

Abstract: The present disclosure relates to a semiconductor device having a lateral resonance structure to coherently reflect light toward the image sensor. The semiconductor device includes an image sensing element arranged within a substrate. A radiation absorption region is arranged within the substrate and above the image sensor, and contains an array of protrusions having a characteristic dimension and an outer border. A resonant structure containing a plurality of deep trench isolation (DTI) structures is disposed on opposing sides of the image sensing element. The (DTI) structures surround the outer border of the array of protrusions. An inner surface of the DTI structure is laterally spaced apart from the outer border of the array of protrusions by a reflective length based on the characteristic dimension of the array of protrusions, thus affecting coherent reflection of light back toward the image sensor.

Abstract: A semiconductor image sensor includes a first substrate including a first front side and a first back side, a first interconnect structure disposed over the first front side of the first substrate, a second substrate including a second front side and a second back side, a second interconnect structure disposed over the second front side of the second substrate, a third substrate including a third front side and a third back side, and a third interconnect structure disposed over the third front side of the third substrate. The first substrate includes a plurality of first sensing devices, and the second substrate includes a plurality of second sensing devices. The second back side of the second substrate faces the first front side of the first substrate, and the second front side of the second substrate faces the third front side of the third substrate.

Abstract: An image sensor is disclosed. The image sensor includes an epitaxial layer, a plurality of plug structures and an interconnect structure. Wherein the plurality of plug structures are formed in the epitaxial layer, and each plug structure has doped sidewalls, the epitaxial layer and the doped sidewalls form a plurality of photodiodes, the plurality of plug structures are used to separate adjacent photodiodes, and the epitaxial layer and the doped sidewalls are coupled to the interconnect structure via the plug structures. An associated method of fabricating the image sensor is also disclosed. The method includes: providing a substrate having a first-type doped epitaxial substrate layer on a second-type doped epitaxial substrate layer; forming a plurality of isolation trenches in the first-type doped epitaxial substrate layer; forming a second-type doped region along sidewalls and bottoms of the plurality of isolation trenches; and filling the plurality of isolation trenches by depositing metal.

Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

Abstract: An igniter for a combustor of a turbomachine includes a fuel inlet in fluid communication with a mixing plenum. The mixing plenum is positioned upstream of a mixing channel. An air inlet is in fluid communication with the mixing plenum and an ignition source is in operative communication with the mixing channel. The igniter may include a mounting flange configured for coupling the igniter to the combustor. The ignition source may be positioned proximate to a downstream end of the mixing channel and upstream of the mounting flange. The mixing channel may define a venturi shape. The venturi shape includes a converging section between an upstream end of the mixing channel and a venturi throat.

Abstract: An image sensor is disclosed. The image sensor includes an epitaxial layer, a plurality of plug structures and an interconnect structure. Wherein the plurality of plug structures are formed in the epitaxial layer, and each plug structure has doped sidewalls, the epitaxial layer and the doped sidewalls form a plurality of photodiodes, the plurality of plug structures are used to separate adjacent photodiodes, and the epitaxial layer and the doped sidewalls are coupled to the interconnect structure via the plug structures. An associated method of fabricating the image sensor is also disclosed. The method includes: providing a substrate having a first-type doped epitaxial substrate layer on a second-type doped epitaxial substrate layer; forming a plurality of isolation trenches in the first-type doped epitaxial substrate layer; forming a second-type doped region along sidewalls and bottoms of the plurality of isolation trenches; and filling the plurality of isolation trenches by depositing metal.

Abstract: An exemplary method includes forming a dummy gate structure over a substrate and forming a set of spacers adjacent to the dummy gate structure. The set of spacers includes spacer liners disposed on sidewalls of the dummy gate structure and main spacers disposed on the spacer liners. The spacer liners include silicon and carbon. The method further includes forming source/drain epitaxy regions over the substrate. The source/drain epitaxy regions are disposed adjacent to the set of spacers, such that the dummy gate structure is disposed between the source/drain epitaxy regions. The method further includes removing the main spacers after forming the source/drain epitaxy regions. The method further includes replacing the dummy gate structure with a gate structure, where the replacing includes removing the dummy gate structure to form a trench defined by the spacers liners, such that the gate structure is formed in the trench.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved protection for the bottom portion of the gate structure. In some embodiments, the method achieves improved protection for gate structure bottom by forming a recess on either side of the gate structure and placing spacers on the side walls of the gate structure, so that the spacers protect the portion of the gate structure below the gate dielectric layer.

Abstract: A pixel sensor device is disclosed. The device includes a shallow trench isolation structure, a well region and a backside isolation structure. The well region and diode region is adjacent to the shallow trench isolation structure. The backside isolation structure is self-aligned with and arranged over the shallow trench isolation structure. The backside isolation structure is adjacent to the diode region.

Abstract: A system and a method for predicting and optimizing remaining hardware life of gas turbine components. Operating parameters of the gas turbine which may impact remaining hardware life are sensed and tracked using a plurality of sensors in communication with a control system including a computing device. Remaining hardware life is predicted using a physics-based hardware lifing model. The hardware lifing model may include an output of a filtration model configured to monitor contaminants based on a pressure drop across a filter. Optimizing the remaining hardware life is achieved by the control system adjusting one or more operation settings of the gas turbine.

Abstract: A system includes a gas turbine system having a first compressor, a combustor, and a turbine, where the first compressor provides a first portion of a discharge air directly to the combustor. The system includes a fluid circuit which receives a fluid comprising a second portion of the discharge air from the first compressor or a combustible fluid and provides the second portion of the discharge air to fuel at a location upstream of the combustor to alter a chemical and physical characteristic of the fuel in an air-fuel mixture that is provided to the combustor.

Abstract: A method for manufacturing a back-side illumination (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor with a vertical transfer gate structure for improved quantum efficiency (QE) and global shutter efficiency (GSE) is provided. A sacrificial dielectric layer is formed over a semiconductor region. A first etch is performed into the sacrificial dielectric layer to form an opening exposing a photodetector in the semiconductor region. A semiconductor column is formed in the opening. A floating diffusion region (FDR) is formed over the semiconductor column and the sacrificial dielectric layer. A second etch is performed into the sacrificial dielectric layer to remove the sacrificial dielectric layer, and to form a lateral recess between the FDR and the photodetector. A gate is formed filling the lateral recess and laterally spaced from the semiconductor column by a gate dielectric layer. The BSI CMOS image sensor resulting from the method is also provided.

Abstract: A pixel sensor device is disclosed. The device includes a shallow trench isolation structure, a well region and a backside isolation structure. The well region and diode region is adjacent to the shallow trench isolation structure. The backside isolation structure is self-aligned with and arranged over the shallow trench isolation structure. The backside isolation structure is adjacent to the diode region.

Abstract: A pixel sensor device is disclosed. The device includes a shallow trench isolation structure, a well region and a backside isolation structure. The well region and diode region is adjacent to the shallow trench isolation structure. The backside isolation structure is self-aligned with and arranged over the shallow trench isolation structure. The backside isolation structure is adjacent to the diode region. An immersion lithographic arrangement is disclosed that compensates for immersion tool drift.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.

Abstract: An exemplary method includes forming a dummy gate structure over a substrate and forming a set of spacers adjacent to the dummy gate structure. The set of spacers includes spacer liners disposed on sidewalls of the dummy gate structure and main spacers disposed on the spacer liners. The spacer liners include silicon and carbon. The method further includes forming source/drain epitaxy regions over the substrate. The source/drain epitaxy regions are disposed adjacent to the set of spacers, such that the dummy gate structure is disposed between the source/drain epitaxy regions. The method further includes removing the main spacers after forming the source/drain epitaxy regions. The method further includes replacing the dummy gate structure with a gate structure, where the replacing includes removing the dummy gate structure to form a trench defined by the spacers liners, such that the gate structure is formed in the trench.

Abstract: A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.

Abstract: A pixel sensor device is disclosed. The device includes a shallow trench isolation structure, a well region and a backside isolation structure. The well region and diode region is adjacent to the shallow trench isolation structure. The backside isolation structure is self-aligned with and arranged over the shallow trench isolation structure. The backside isolation structure is adjacent to the diode region. An immersion lithographic arrangement is disclosed that compensates for immersion tool drift.

Abstract: A method for manufacturing a back-side illumination (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor with a vertical transfer gate structure for improved quantum efficiency (QE) and global shutter efficiency (GSE) is provided. A sacrificial dielectric layer is formed over a semiconductor region. A first etch is performed into the sacrificial dielectric layer to form an opening exposing a photodetector in the semiconductor region. A semiconductor column is formed in the opening. A floating diffusion region (FDR) is formed over the semiconductor column and the sacrificial dielectric layer. A second etch is performed into the sacrificial dielectric layer to remove the sacrificial dielectric layer, and to form a lateral recess between the FDR and the photodetector. A gate is formed filling the lateral recess and laterally spaced from the semiconductor column by a gate dielectric layer. The BSI CMOS image sensor resulting from the method is also provided.