Abstract: Embodiments of the invention include a voltage-switching MTJ cell structure that includes two sub-MTJs in series. Each free layer can be switched independently from the other. Each sub-MTJ has a high and a low resistance state and the MTJ cell structure can have three or four discrete resistance states. By taking advantage of the electrical field induced anisotropy combining with the spin torque effect, free layer-1 and free layer-2 can be controlled individually by voltage pulses having selected sign (polarity) and amplitude characteristics. The MTJ cell structure can be used as a fully functional logic cell with two input bit values corresponding to the high or low resistance of the two sub-MTJ structures and the output of a logical operation, e.g. an XOR function, determined by the resistance state of each MTJ cell.

Abstract: Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step.

Abstract: The present invention is directed to an STT-MRAM device including a plurality of magnetic tunnel junction (MTJ) memory elements. Each of the memory elements comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween; and a magnetic fixed layer separated from the magnetic reference layer structure by an anti-ferromagnetic coupling layer.

Abstract: Resistive memory cell array fabricated with unit areas able to be scaled down to 4 F2, where F is minimum feature size in a technology node are described. Memory cells in a pair of cells commonly include a pair of buried sources in the bottom of trenches formed in a silicon substrate. The source line is shared with an adjacent cell. A pair of gate electrodes provides a vertical channel on a sidewall of the trench. A buried word line connects the bottom of the gates on the sidewall overlying the source wherein the word line is looped at the end of the array. A drain, which is self-aligned to the gate, is formed by implantation/doping the surface of the silicon before patterning the trenches. A contact is formed on top of the drain and the resistive memory element is fabrication on the contact.

Abstract: A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts.

Abstract: The present invention is directed to a method for reading and writing an STT-MRAM multi-level cell (MLC), which includes a plurality of MTJ memory elements coupled in series. The method detects the resistance states of individual MTJ memory elements in an MLC by sequentially writing each memory element to the low resistance state in order of ascending parallelizing write current threshold. If a written element switches the resistance state thereof after the write step, then the written element was in the high resistance state prior to the write step. Otherwise, the written element was in the low resistance state prior to the write step. The switching of the resistance state can be ascertained by comparing the resistance or voltage values of the plurality of memory elements before and after writing each of the plurality of memory elements in accordance with the embodiments of the present invention.

Abstract: The present invention relates to memory devices incorporating therein a novel memory cell architecture which includes an array of selection transistors sharing a common channel and method for making the same. A memory device comprises a semiconductor substrate having a first type conductivity, a plurality of drain regions and a common source region separated by a common plate channel in the substrate, and a selection gate disposed on top of the plate channel with a gate dielectric layer interposed therebetween. The plurality of drain regions and the common source region have a second type conductivity opposite to the first type provided in the substrate.

Abstract: The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto.

Abstract: Use of a multilayer etching mask that includes a stud mask and a removable spacer sleeve for MTJ etching to form a bottom electrode that is wider than the rest of the MTJ pillar is described. The first embodiment of the invention described includes a top electrode and a stud mask. In the second and third embodiments the stud mask is a conductive material and also serves as the top electrode. In embodiments after the stud mask is formed a spacer sleeve is formed around it to initially increase the masking width for a phase of etching. The spacer is removed for further etching, to create step structures that are progressively transferred down into the layers forming the MTJ pillar. In one embodiment the spacer sleeve is formed by net polymer deposition during an etching phase.

Abstract: The present invention is directed to a field effect transistor having a trough channel structure. The transistor comprises a semiconductor substrate of a first conductivity type having a trough structure therein with the trough structure extending along a first direction; an insulating layer formed on top of the trough structure; a gate formed on top of the insulator layer in a second direction perpendicular to the first direction and extending over and into the trough structure with a gate dielectric layer interposed therebetween; a source and a drain of a second conductivity type opposite to the first conductivity type formed in the trough structure on opposite sides of the gate.

Abstract: A STTMRAM element includes a magnetization layer made of a first free layer and a second free layer, separated by a non-magnetic separation layer (NMSL), with the first and second free layers each having in-plane magnetizations that act on each other through anti-parallel coupling. The direction of the magnetization of the first and second free layers each is in-plane prior to the application of electrical current to the STTMRAM element and thereafter, the direction of magnetization of the second free layer becomes substantially titled out-of-plane and the direction of magnetization of the first free layer switches. Upon electrical current being discontinued to the STTMRAM element, the direction of magnetization of the second free layer remains in a direction that is substantially opposite to that of the first free layer.

Abstract: High-frequency resonance method is used to measure magnetic parameters of magnetic thin film stacks that show magnetoresistance including MTJs and giant magnetoresistance spin valves. The thin film sample can be unpatterned. Probe tips are electrically connected to the surface of the film (or alternatively one probe tip can be punched into the thin film stack) and voltage measurements are taken while injecting high frequency oscillating current between them to cause a change in electrical resistance when one of the layers in the magnetic film stack changes direction. A measured resonance curve can be determined from voltages at different current frequencies. The damping, related to the width of the resonance curve peak, is determined through curve fitting. In embodiments of the invention a variable magnetic field is also applied to vary the resonance frequency and extract the magnetic anisotropy and/or magnetic saturation of the magnetic layers.

Abstract: A spin transfer torque memory random access memory (STTMRAM) element is capable of switching states when electrical current is applied thereto for storing data and includes the following layers. An anti-ferromagnetic layer, a fixed layer formed on top of the anti-ferromagnetic layer, a barrier layer formed on top of the second magnetic layer of the fixed layer, and a free layer including a first magnetic layer formed on top of the barrier layer, a second magnetic layer formed on top of the first magnetic layer, a nonmagnetic insulating layer formed on top of the second magnetic layer and a third magnetic layer formed on top of the non-magnetic insulating layer. A capping layer is formed on top of the non-magnetic insulating layer.

Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer, which can be a single layer structure or a synthetic multi-layer structure, formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A tuning layer is formed on top of the free layer and a fixed layer is formed on top of the tuning layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field.

Abstract: A spin-torque transfer magnetic random access memory (STTMRAM) element employed to store a state based on the magnetic orientation of a free layer, the STTMRAM element is made of a first perpendicular free layer (PFL) including a first perpendicular enhancement layer (PEL). The first PFL is formed on top of a seed layer. The STTMRAM element further includes a barrier layer formed on top of the first PFL and a second perpendicular reference layer (PRL) that has a second PEL, the second PRL is formed on top of the barrier layer. The STTMRAM element further includes a capping layer that is formed on top of the second PRL.

Abstract: A testing method is described that applies a sequence external magnetic fields of varying strength to MRAM cells (such as those with MTJ memory elements) in chips or wafers to selectively screen out cells with low or high thermal stability factor. The coercivity (Hc) is used as a proxy for thermal stability factor (delta). In the various embodiments the sequence, direction and strength of the external magnetic fields is used to determine the high coercivity cells that are not switched by a normal field and the low coercivity cells that are switched by a selected low field. In some embodiment the MRAM's standard internal electric current can be used to switch the cells. Standard circuit-based resistance read operations can be used to determine the response of each cell to these magnetic fields and identify the abnormal high and low coercivity cells.

Abstract: Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

Abstract: Various embodiments of the invention relate to etching processes used in fabrication of MTJ cells in an MRAM device. The various embodiments can be used in combination with each other. The first embodiment adds a hard mask buffer layer between a hard mask and a top electrode. The second embodiment uses a multilayered etching hard mask. The third embodiment uses a multilayered top electrode structure including a first Cu layer under a second layer such as Ta. The fourth embodiment is a two-phase etching process used for the bottom electrode to remove re-deposited material while maintaining a more vertical sidewall etching profile. In the first phase the bottom electrode layer is removed using carbonaceous reactive ion etching until the endpoint. In the second phase an inert gas and/or oxygen plasma is used to remove the polymer that was deposited during the previous etching processes.

Abstract: A spin transfer torque magnetic random access memory (STTMRAM) magnetic tunnel junction (MTJ) stack includes layers to which when electric current is applied cause switching of the direction of magnetization of at least one of the layer. The STTMRAM MTJ stack includes a reference layer (RL) with a direction of magnetization that is fixed upon manufacturing of the STTMRAM MTJ stack, a junction layer (JL) formed on top of the RL, a free layer (FL) formed on top of the JL. The FL has a direction of magnetization that is switchable relative to that of the RL upon the flow of electric current through the spin transfer torque magnetic random access memory (STTMRAM) magnetic tunnel junction (MTJ) stack. The STTMRAM MTJ stack further includes a spin confinement layer (SCL) formed on top of the FL, the SCL made of ruthenium.

Abstract: A spin-torque transfer memory random access memory (STTMRAM) element, employed in a STTMRAM array, receives electric current for storage of digital information, the STTMRAM element has a magnetic tunnel junction (MTJ). The MTJ includes an anti-ferromagnetic (AF) layer, a fixed layer having a magnetization that is substantially fixed in one direction and that comprises a first magnetic layer, an AF coupling layer and a second magnetic layer, a barrier layer formed upon the fixed layer, and a free layer. The free layer is synthetic and has a high-polarization magnetic layer, a low-crystallization magnetic layer, a non-magnetic separation layer, and a magnetic layer, wherein during a write operation, a bidirectional electric current is applied across the STTMRAM element to switch the magnetization of the free layer between parallel and anti-parallel states relative to the magnetization of the fixed layer.