Patents by Inventor Yin Liu

Yin Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12289979
    Abstract: The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes a mask pattern made up of a number of openings passing through the masking wafer to correspond to a predetermined deposition pattern to be formed on the target wafer. A deposition chamber is configured to receive the first and second wafer-mounting frames, when the first and second wafer-mounting frames are clamped together to retain the target wafer and the masking wafer. The deposition chamber includes a material deposition source configured to deposit material from the material deposition source through the number of openings in the mask pattern to form the material in the predetermined deposition pattern on the target wafer.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: April 29, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Chia-Shiung Tsai, Xin-Hua Huang, Yu-Hsing Chang, Yeong-Jyh Lin
  • Publication number: 20250117642
    Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.
    Type: Application
    Filed: December 16, 2024
    Publication date: April 10, 2025
    Inventors: Win-San KHWA, Yu-Der CHIH, Yi-Chun SHIH, Chien-Yin LIU
  • Publication number: 20250118587
    Abstract: In some embodiments, the present disclosure relates to a method that includes aligned a first wafer with a second wafer. The second wafer is spaced apart from the first wafer. The first wafer is arranged on a first electrostatic chuck (ESC). The first ESC has electrostatic contacts that are configured to attract the first wafer to the first ESC. Further, the second wafer is brought toward the first wafer to directly contact the first wafer at an inter-wafer interface. The inter-wafer interface is localized to a center of the first wafer. The second wafer is deformed to gradually expand the inter-wafer interface from the center of the first wafer toward an edge of the first wafer. The electrostatic contacts of the first ESC are turned OFF such that the first and second wafers are bonded to one another by the inter-wafer interface.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 10, 2025
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Chang-Chen Tsao
  • Patent number: 12255062
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Grant
    Filed: November 14, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20250079492
    Abstract: A plant microbial fuel cell includes a planting container, a plant, a cathode and an anode. The planting container has a culture medium therein, and a microbial population is in the culture medium. The plant is grown in the culture medium in the planting container. The cathode is disposed on a surface of the culture medium, and the anode is arranged in the culture medium close to roots of the plant. The anode includes a porous carbon material prepared from coffee grounds, and thus the overall cost of the plant microbial fuel cell may be greatly reduced, and the porous carbon material is easy to process and has high biocompatibility.
    Type: Application
    Filed: October 19, 2023
    Publication date: March 6, 2025
    Applicant: National Tsing Hua University
    Inventors: Yao-Yu Lin, Hsin-Tien Li, Heng-An Su, Tzu-Yin Liu, Han-Yi Chen
  • Publication number: 20250079853
    Abstract: A power generating device and a power supplying method thereof are provided. The power generating device includes a battery set, a charge storage device, a charger and a voltage converter. The battery set has microbial fuel cell and/or solar battery, and is configured to generate a supply voltage. The charger generates a charging voltage according to the supply voltage, and provides the charging voltage through a first resistor to charge the charge storage device. The voltage converter converts a storage voltage provided by the charge storage device to generate a driving voltage, and provides the driving voltage to drive a load.
    Type: Application
    Filed: October 20, 2023
    Publication date: March 6, 2025
    Applicant: National Tsing Hua University
    Inventors: Chao-I Liu, Heng-An Su, I-Chu Lin, Yao-Yu Lin, Chia-Chieh Hsu, Hsin-Tien Li, Tzu-Yin Liu, Han-Yi Chen
  • Patent number: 12211727
    Abstract: In some embodiments, the present disclosure relates to a method that includes aligned a first wafer with a second wafer. The second wafer is spaced apart from the first wafer. The first wafer is arranged on a first electrostatic chuck (ESC). The first ESC has electrostatic contacts that are configured to attract the first wafer to the first ESC. Further, the second wafer is brought toward the first wafer to directly contact the first wafer at an inter-wafer interface. The inter-wafer interface is localized to a center of the first wafer. The second wafer is deformed to gradually expand the inter-wafer interface from the center of the first wafer toward an edge of the first wafer. The electrostatic contacts of the first ESC are turned OFF such that the first and second wafers are bonded to one another by the inter-wafer interface.
    Type: Grant
    Filed: March 29, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Chang-Chen Tsao
  • Patent number: 12205017
    Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: January 21, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Win-San Khwa, Yu-Der Chih, Yi-Chun Shih, Chien-Yin Liu
  • Publication number: 20240371697
    Abstract: A method of the present disclosure includes forming a fin-shaped structure including a plurality of semiconductor layers, a first hard mask layer, a second hard mask layer, and a third hard mask layer, forming a patterned masking layer having a mask portion and a window portion, wherein the third hard mask layer is exposed through the window portion, performing a first etch process to expose the second hard mask layer through the window portion, performing a second etch process to etch the exposed second hard mask layer and to leave behind second hard mask layer residues, performing a third etch process to remove the second hard mask layer residues, etching the plurality of semiconductor layers in the fin-shaped structure through the window portion to divide the fin-shaped structure into a first segment and a second segment, and forming an isolation feature around the first segment and the second segment.
    Type: Application
    Filed: July 11, 2024
    Publication date: November 7, 2024
    Inventors: Han-Yu Tsai, Zu-Yin Liu, You-Ting Lin, Jiun-Ming Kuo, Kuo-Chin Liu
  • Publication number: 20240330675
    Abstract: Validity of a trained artificial intelligence model is verified. The verifying the validity includes generating a training dataset from the trained artificial intelligence model using reverse data generation of the trained artificial intelligence model. The training dataset generated using the reverse data generation is compared with a test dataset used to evaluate the trained artificial intelligence model. The comparing is to determine a relationship between the training dataset that was generated and the test dataset. Data from the test dataset determined to have a predefined relationship with the training dataset is removed to obtain a new test dataset. The new test dataset is used to verify the validity of the trained artificial intelligence model.
    Type: Application
    Filed: March 27, 2023
    Publication date: October 3, 2024
    Inventors: Zhong Fang YUAN, Tong LIU, Shuang Yin LIU, Jun WANG, Yan Fen LIU
  • Publication number: 20240312788
    Abstract: A method includes forming a fin protruding from a substrate, the fin including an epitaxial stack over a fin base and a hard mask layer over the epitaxial stack, the epitaxial stack including first and second semiconductor layers of different material compositions, performing a first etching process to etch the hard mask layer, the first etching process including applying a first combination of etchants, performing a second etching process to etch the epitaxial stack, the second etching process including applying a second combination of etchants, and performing a third etching process to etch the fin base, the third etching process including applying a third combination of etchants. The first, second, and third combinations of etchants are different from each other.
    Type: Application
    Filed: August 18, 2023
    Publication date: September 19, 2024
    Inventors: Shin-Li WANG, Szu-Ping LEE, Zu-Yin LIU, You-Ting LIN, Jiun-Ming KUO, Chun-Hung LEE, Yuan-Ching PENG
  • Publication number: 20240304657
    Abstract: A semiconductor device includes a substrate, a first gate, a plurality of second gates and a resistor. The substrate is defined with an active region and a resistor region. The first gate is disposed in the active region. The first gate has a first length extending along a first direction and a second length extending along a second direction. The plurality of second gates are disposed in the resistor region. Each of the second gates has a third length extending along the first direction and a fourth length extending along the second direction. The first length is equal to the third length, and the second length is equal to the fourth length. The resistor is disposed on the plurality of second gates.
    Type: Application
    Filed: March 29, 2023
    Publication date: September 12, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Chun Teng, Ming-Che Tsai, Ping-Chia Shih, Yi-Chang Huang, Wen-Lin Wang, Yu-Fan Hu, Ssu-Yin Liu, Yu-Nong Chen, Pei-Tsen Shiu, Cheng-Tzung Tsai
  • Patent number: 12080603
    Abstract: A method of the present disclosure includes forming a fin-shaped structure including a plurality of semiconductor layers, a first hard mask layer, a second hard mask layer, and a third hard mask layer, forming a patterned masking layer having a mask portion and a window portion, wherein the third hard mask layer is exposed through the window portion, performing a first etch process to expose the second hard mask layer through the window portion, performing a second etch process to etch the exposed second hard mask layer and to leave behind second hard mask layer residues, performing a third etch process to remove the second hard mask layer residues, etching the plurality of semiconductor layers in the fin-shaped structure through the window portion to divide the fin-shaped structure into a first segment and a second segment, and forming an isolation feature around the first segment and the second segment.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Yu Tsai, Zu-Yin Liu, You-Ting Lin, Jiun-Ming Kuo, Kuo-Chin Liu
  • Publication number: 20240189878
    Abstract: A waste liquid-crystalline glass recycling system includes a liquid-crystalline glass film removing module and a liquid-crystalline glass separation module connected with the liquid-crystalline glass film removing module. The liquid-crystalline glass film removing module includes a crushing device and a film removal device. The crushing device is configured to crush a liquid crystal panel. The film removal device is connected with the crushing device, and is configured to separate the liquid crystal panel into a glass-liquid crystal mixture and optical film debris. The liquid-crystalline glass separation module is connected with the liquid-crystalline glass film removing module, and is configured to separate the glass-liquid crystal mixture into glass sand and a liquid crystal mixture by using a solvent, in which the liquid crystal mixture includes the solvent.
    Type: Application
    Filed: August 8, 2023
    Publication date: June 13, 2024
    Inventors: Hsiang-Ming WANG, Pei-Yin Liu, Po-Wen Chi
  • Patent number: 11999831
    Abstract: An aluminum borate whisker reinforced and toughened non-metallic matrix composite is provided, which specifically includes a non-metallic material reinforced and toughened with aluminum borate whiskers. The composite exhibits a higher bending strength and fracture toughness and a higher wear resistance. A method for preparing the composite is also provided. The method includes mixing the aluminum borate whiskers and the non-metallic material to form a mixture; and sintering the mixture by a vacuum hot press method, or molding the mixture.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: June 4, 2024
    Assignees: Chongqing University of Science and Technology, Chongqing Stio Measurement & Control Tech Co., Ltd
    Inventors: Bi Jia, Jinliang Shi, Zhigang Zou, Yong Zhou, Yongjiang Di, Yin Liu, Yue Shi, Huichao He, Rong Wang, Xueyi Wang, Hao Tian, Jun Zhu, Rui Tang, Xingyu Chen, Danxia Zhang
  • Publication number: 20240178263
    Abstract: A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: Ping-Yin Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen, Pin-Nan Tseng
  • Publication number: 20240118349
    Abstract: The disclosure discloses a battery device, a detection method thereof, a method and device for screening battery cells. The characteristic values are determined according to parameters of two peaks in the frequency-domain impedance diagram. The characteristic values may reflect the magnitude of charge transfer impedance and diffusion impedance in each battery cell, then reflect the characteristics of the interface and characteristics of solid phase particles during charging and discharging, and further reflect the health and performance of battery cells. The battery set screened in this way still have good consistency after storage and shelving, and the consistency between battery cells will not deteriorate after storage for a period of time, so that the battery device may have better performance.
    Type: Application
    Filed: December 1, 2022
    Publication date: April 11, 2024
    Applicant: CALB Co., Ltd.
    Inventors: Ruijun Ma, Fengsong Fan, Shengjie Wang, Yin Liu, Kui Li
  • Patent number: D1033321
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: July 2, 2024
    Assignee: Ningbo Yonk Machiery Co., Ltd.
    Inventor: Yin Liu
  • Patent number: D1041278
    Type: Grant
    Filed: May 10, 2024
    Date of Patent: September 10, 2024
    Inventor: Yin Liu
  • Patent number: D1053688
    Type: Grant
    Filed: August 28, 2024
    Date of Patent: December 10, 2024
    Inventor: Yin Liu