Abstract: Provided are a human LIFR antigen binding protein, a preparation method therefor, and an application thereof. A series of human LIFR antibodies having biological functions are obtained using human LIFR-ECD protein immune H2L2 humanized antibody transgenic mice by means of single B cell cloning technology (SBC), single B cell sequencing analysis, and Fc recombination. The method greatly improves the discovery efficiency and the yield of antibody drugs, and the obtained human LIFR antibody has good affinity and can block the binding of huLIF proteins to huLIFR/gp130 cells, thereby inhibiting signaling pathways such as STAT3, further inhibiting the growth of tumors, and achieving the purpose of tumor prevention and treatment.

Abstract: An electronic device is provided. The electronic device includes an optical sensing module that includes an optical sensor array. The optical sensor array includes at least one optical sensor, at least one transparent layer disposed on the optical sensor array, and a microlens array. The microlens array includes at least one microlens and is disposed on the transparent layer.

Abstract: The present disclosure relates to a processing tool that includes a first wafer-mounting frame and a second wafer-mounting frame. The first wafer-mounting frame is configured to retain a target wafer. The second wafer-mounting frame is configured to retain a masking wafer. The masking wafer includes a mask pattern made up of a number of openings passing through the masking wafer to correspond to a predetermined deposition pattern to be formed on the target wafer. A deposition chamber is configured to receive the first and second wafer-mounting frames, when the first and second wafer-mounting frames are clamped together to retain the target wafer and the masking wafer. The deposition chamber includes a material deposition source configured to deposit material from the material deposition source through the number of openings in the mask pattern to form the material in the predetermined deposition pattern on the target wafer.

Abstract: A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a plurality of semiconductor layers vertically stacked over a substrate, wherein the semiconductor layers are vertically spaced apart from each other; forming a source/drain epitaxial structure on sides of the semiconductor layers, wherein the source/drain epitaxial structure is doped with a p-type doping species; implanting fluorine ions into the source/drain epitaxial structure; after implanting fluorine ions into the source/drain epitaxial structure, performing an annealing process to diffuse the p-type doping species into a side region of a topmost one of the semiconductor layers; and forming a source/drain contact over the source/drain epitaxial structure.

Abstract: A method, including: monitoring resource utilization of an operating system (OS) with applications utilizing larger pages; determining the monitored resource utilization is greater than a threshold resource utilization; in response to the determining the monitored resource utilization is greater than a threshold resource utilization, determining a respective larger pages index value for each of the applications utilizing larger pages; and turning off larger pages utilization of a subset of the applications utilizing larger pages, wherein the subset comprises a predefined number of the applications utilizing larger pages that have highest determined larger pages index values.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are described herein. A method includes implanting neutral elements into a dielectric layer, an etch stop layer, and a metal feature, the dielectric layer being disposed over the etch stop layer and the metal feature being disposed through the dielectric layer and the etch stop layer. The method further includes using a germanium gas as a source for the neutral elements and using a beam current above 6.75 mA to implant the neutral elements.

Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

Abstract: The use of Black Solider Fly Larvae as Palatant/Palatability Enhancer for use in edible pet products This invention disclosed a palatability enhancer for edible pet products using black solider fly (Hermetia illucens) larvae, wherein the black solider fly larvae are collected following the commercial farming, the greater part of the materials being processed for safety and size reduced as necessary, at 10.0%-80.0%. The palatability enhancer may also include at least one of the following: Cysteine, Arginine, Alanine, Glutamine, Aspartic acid, Glycine, Phenylalanine, Isoleucine, Histidine, Vitamin B1, and a reducing sugar, at 0.1%-10.0% by weight.

Abstract: A speaker assembly including a first speaker comprising a first diaphragm and a first voice coil movably coupled to a first magnet assembly, wherein the first diaphragm faces a first direction, the first voice coil moves along a first axis in the first direction when driven by an audio signal and the first magnet assembly is coupled to a fixed structure by a first compliant mounting member; and a second speaker laterally offset from the first speaker and including a second diaphragm and a second voice coil movably coupled to a second magnet assembly, wherein the second diaphragm faces a second direction different from the first direction, the second voice coil moves along a second axis in the second direction when driven by an audio signal and the second magnet assembly is coupled to the fixed structure by a second compliant mounting member.

Abstract: In some embodiments, the present disclosure relates to a method that includes aligned a first wafer with a second wafer. The second wafer is spaced apart from the first wafer. The first wafer is arranged on a first electrostatic chuck (ESC). The first ESC has electrostatic contacts that are configured to attract the first wafer to the first ESC. Further, the second wafer is brought toward the first wafer to directly contact the first wafer at an inter-wafer interface. The inter-wafer interface is localized to a center of the first wafer. The second wafer is deformed to gradually expand the inter-wafer interface from the center of the first wafer toward an edge of the first wafer. The electrostatic contacts of the first ESC are turned OFF such that the first and second wafers are bonded to one another by the inter-wafer interface.

Abstract: Techniques are described to indicate traffic awareness information by a network device. An example wireless communication method includes communicating, by a first network function of a network node, traffic awareness information to a second network function of the network node, wherein the traffic awareness information includes traffic characteristics of one or more quality of service (QoS) flows between the network node and a communication node.

Abstract: A method includes: forming a stack of nanostructures over a substrate; forming a source/drain opening adjacent the stack of nanostructures; forming a semiconductor layer in the source/drain opening; forming an amorphous semiconductor layer by performing an ion implantation on the semiconductor layer; and forming a recrystallized source/drain by annealing the amorphous semiconductor layer.

Abstract: Techniques are described to trigger, by a first entity, a process by which one or more interfaces are established over a user plane or a control plane between the first entity and a second entity, where the triggering is based on a first communication of a first message between the first entity and the second entity, and where the one or more interfaces are used for data communication between the first entity and the second entity; and establish, by the first entity, the one or more interfaces by performing a second communication of a second message between the first entity and the second entity in response to the first communication.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.

Abstract: Provided are a data processing method and device, and a storage medium. The method includes: receiving configuration information of a blockchain from a second network element, where the configuration information includes: application layer blockchain on-chaining auxiliary information, or application layer blockchain uplink auxiliary information and application layer blockchain configuration information; and putting terminal application layer information on the blockchain according to the application layer blockchain on-chaining auxiliary information.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

Abstract: A wireless communication method for use in a wireless terminal is disclosed. The method comprises performing, with a wireless network node, a data communication, wherein time information associated with the data communication and a time information identification of the time information are included in a Packet Data Convergence Protocol (PDCP) packet data unit (PDU) of the data communication.

Abstract: This disclosure relates generally to a method, device, and system for congestion control in a wireless network. One method performed by a first network element is disclosed. The method may include providing, to a second network element, a DTX configuration for a cell associated with the second network element; providing, to a wireless device served by the cell and based on the DTX configuration, a CDRX configuration for the wireless device; and transmitting data to the wireless device according to the DTX configuration.

Abstract: A method includes forming a metallic feature, forming an etch stop layer over the metallic feature, implanting the metallic feature with a dopant, forming a dielectric layer over the etch stop layer, performing a first etching process to etch the dielectric layer and the etch stop layer to form a first opening, performing a second etching process to etch the metallic feature and to form a second opening in the metallic feature, wherein the second opening is joined with the first opening, and filling the first opening and the second opening with a metallic material to form a contact plug.