Abstract: A method for operating a memory device is provided. The memory device includes a first word line, a second word line, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first word line and the second word line. A first pass voltage is applied to the first dummy word line in a program operation. A second pass voltage is applied to the second dummy word line in the program operation. The first pass voltage is different from the second pass voltage.

Abstract: According to one aspect, a method of operating a memory is provided. The method may include applying a first power supply voltage to a common source during a program precharge process. The method may include applying a first voltage to a first bottom gate line and applying a second voltage to a second bottom gate line starting at a first moment of the program precharge process. The method may include applying a second power supply voltage to the first bottom gate line and applying a third voltage to the second bottom gate line after the first moment of the program precharge process.

Abstract: A memory device includes a memory cell array including a source layer, a bottom select gate layer, and a gate layer, and the bottom select gate layer is located between the source layer and the gate layer, wherein the bottom select gate layer includes a plurality of bottom select gates, and a bottom select gate of a first memory string and a bottom select gate of a second memory string are connected with a same select line; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to apply a selection voltage to the select line to control the first memory string and the second memory string.

Abstract: According to one aspect, a method of operating a memory is provided. The method may include applying a first power supply voltage to a common source during a program precharge process. The method may include applying a first voltage to a first bottom gate line and applying a second voltage to a second bottom gate line starting at a first moment of the program precharge process. The method may include applying a second power supply voltage to the first bottom gate line and applying a third voltage to the second bottom gate line after the first moment of the program precharge process.

Abstract: A non-volatile memory device includes a memory string, a select gate line coupled to the memory string, word lines coupled to the memory string and including a selected word line, and a control circuit coupled to the select gate line and the word lines, and configured to apply word line pre-pulse signals to at least two groups of the word lines disposed between the select gate line and the selected word line during a pre-charge period. The at least two groups of the word lines include a first group and a second group disposed between the first group and the select gate line. A voltage level of a second word line pre-pulse signal applied to the second group is greater than a voltage level of a first word line pre-pulse signal applied to the first group. A voltage level of at least one word line pre-pulse signal of the word line pre-pulse signals is greater than 0.

Abstract: Disclosed are an array substrate, a preparation method, a display panel, and a display device. A pixel limiting layer includes a first limiting sublayer and a second limiting sublayer which contact each other, and a first height of the first limiting sublayer in a direction perpendicular to a plane where a base substrate is located is greater than a second height of the second limiting sublayer in the direction perpendicular to the plane where the base substrate is located. Thus, when light emitting layers are formed in pixel openings by an ink jet printing process, light emitting layers having different colors can be spaced apart by the first limiting sublayer.

Abstract: The present disclosure provides a memory device, a memory system, and an operation method of a memory device, and relates to the technical field of semiconductor chips. The memory device includes a memory cell array including a source layer, a bottom select gate layer, and a gate layer, and the bottom select gate layer is located between the source layer and the gate layer, wherein the bottom select gate layer includes a plurality of bottom select gates, and a bottom select gate of a first memory string and a bottom select gate of a second memory string are connected with a same select line; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to apply a selection voltage to the select line to control the first memory string and the second memory string.

Abstract: The embodiment of the present application provides an array substrate, display panel and display device.

Abstract: In some aspects, a memory device is provided. The memory device includes a plurality of memory strings and a peripheral circuit. One of the memory strings includes memory cells, a select transistor coupled to a select line and a bit line, and a dummy cell coupled to a dummy word line and arranged between the select transistor and the memory cells. The peripheral circuit is coupled to the memory strings and configured to, in a pre-pulse period of a program operation, maintain a first voltage on the select line to retain an on-state of the select transistor and apply a second voltage to the dummy word line to turn off the dummy cell. After applying the second voltage to the dummy word line, the peripheral circuit is further configured to apply a third voltage to the select line to turn off the select transistor.

Abstract: Provided are an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a pixel defining layer including first sub-pixel opening columns and second sub-pixel opening columns that are alternately arranged; the first sub-pixel opening column includes at least two types of sub-pixel openings having different illumination colors; an area of the sub-pixel opening in the second sub-pixel opening column is greater than that of the sub-pixel opening in the first sub-pixel column; in the first sub-pixel opening column, the pixel defining layer between adjacent sub-pixel openings having the same illumination color is made of a lyophilic material, and the pixel defining layer between adjacent sub-pixel openings having different illumination colors is made of a material that is switched between a lyophilic property and a lyophobic property as an external condition changes.

Abstract: Disclosed in the present disclosure is a rich-media document auxiliary generation apparatus. The apparatus comprises a material extraction module, a theme sorting module, a semantic retrieval module, a structured data text generation module, an illustration recommendation module and a video composition module. The present disclosure uses intelligent means to assist a user to efficiently generate a high-quality rich-media composite document, thereby quickly and accurately describing a theme event in an all-round way.

Abstract: A semiconductor device includes a memory string including a first memory cell, a second memory cell, and a third memory cell between the first memory cell and the second memory cell, word lines including a first word line coupled to the first memory cell, a second word line coupled to the second memory cell, a third word line coupled to the third memory cell, and a peripheral circuit coupled to the word lines. The peripheral circuit is configured to in a programming phase, apply a first pass voltage to the second word line, and after applying the first pass voltage to the second word line, apply a programming voltage to the first word line to program the first memory cell.

Abstract: In some aspects, a memory device is provided. The memory device includes a plurality of memory strings and a peripheral circuit. One of the memory strings includes memory cells, a select transistor coupled to a select line and a bit line, and a dummy cell coupled to a dummy word line and arranged between the select transistor and the memory cells. The peripheral circuit is coupled to the memory strings and configured to, in a pre-pulse period of a program operation, maintain a first voltage on the select line to retain an on-state of the select transistor and apply a second voltage to the dummy word line to turn off the dummy cell. After applying the second voltage to the dummy word line, the peripheral circuit is further configured to apply a third voltage to the select line to turn off the select transistor.

Abstract: A memory device includes a first deck including a first set of word lines, a second deck including a second set of word lines, and a controller. The controller is coupled to the first deck and configured to during a time period of programming memory cells coupled to a first word line of the first set of word lines, apply a program voltage to the first word line, apply a first pass voltage to a second word line of the second set of word lines during the time period, and apply a second pass voltage to a third word line of the first set of word lines during the time period. The third word line is between the first word line and the second word line. The second pass voltage is greater than the first pass voltage.

Abstract: The present disclosure provides a transparent display panel and method for manufacturing the same and a display device. The transparent display panel includes pixel units arranged in an array, and the pixel unit includes a light-emitting area and a transparent area. The pixel unit includes a pixel defining layer disposed in the light-emitting area and defining a plurality of opening areas. A light-emitting device is disposed in the opening area. The pixel unit further includes a transparent film layer disposed in the transparent area and being of a hydrophobic material. The transparent film layer includes a groove and an inclined channel, and the channel connects the groove with any one of the opening areas. A bottom surface of the groove is higher than a bottom surface of the opening area, and an area of the groove is greater than that of the opening area connected with the channel.

Abstract: Provided is a display panel. The display panel includes a base substrate, a light-emitting layer, a package layer, and a light conversion layer that are successively stacked. The light conversion layer includes a plurality of light conversion units arranged in an array and a plurality of micro-mirror structures. The plurality of light conversion units include a plurality of first light conversion units, and the plurality of micro-mirror structures include a plurality of first micro-mirror structures surrounding the first light conversion units. Each of the first micro-mirror structures is configured to reflect at least a portion of light from an interior of each of the first light conversion units.

Abstract: A memory device includes word lines and a control circuit coupled to the word lines. The control circuit is configured to apply a programming voltage to a first word line of the word lines, apply a first pass voltage to a second word line of the word lines, apply a second pass voltage to a third word lines of the word lines, the second word line and the third word line are located on opposite sides of the first word line, apply a third pass voltage to a fourth word line of the word lines, the second word line is located between the fourth word line and the first word line, and apply a fourth pass voltage to a fifth word line of the word lines. The third word line is located between the fifth word line and the first word line. The first pass voltage is different from the third pass voltage. The second pass voltage is different from the fourth pass voltage.

Abstract: A programming method and a semiconductor device are provided. The semiconductor device includes a memory string that includes a plurality of first memory cells and a first dummy cell stacked in sequence, and each first memory cell is connected to a respective word line, and a gate of the first dummy cell is connected to a first dummy word line. The method includes: in a programming phase, applying a first pass voltage to a word line corresponding to a first unprogrammed memory cell, wherein the first unprogrammed memory cell is an unprogrammed memory cell of the plurality of first memory cells separated from a to-be-programmed memory cell by a first preset number of first memory cells; and after applying the first pass voltage to the word line corresponding to the first unprogrammed memory cell, applying a programming voltage to the word line corresponding to the to-be-programmed memory cell.

Abstract: In certain aspects, a memory device includes memory strings each including a drain select gate (DSG) transistor, memory cells, and a source select gate (SSG) transistor, and a peripheral circuit coupled to the memory strings. The peripheral circuit is configured to, in a program operation, program a select memory cell of the memory cells in a select memory string of the memory strings, and inhibit an unselect memory cell of the memory cells in an unselect memory string of the memory strings. The peripheral circuit includes a word line driver configured to in a pre-pulse period and a post-pulse period in a first loop of the program operation, turn off the DSG transistor in the unselect memory string, and in at least one of a pre-pulse period or a post-pulse period in a second loop of the program operation after the first loop, turn on the DSG transistor in the unselect memory string.

Abstract: An array substrate is provided, including: multiple columns of pixel units on a substrate, including multiple first and second pixel unit columns alternately in a row direction; each first/second pixel unit column includes multiple first/second pixel units in a column direction; first and second pixel units adjacent to each other are staggered in the row direction in adjacent first and second pixel unit columns. Each first/second pixel unit includes at least two sub-pixels of different colors in multiple columns, and each column of sub-pixels have a same color; each first/second pixel unit includes one rectangular sub-pixel and at least one non-rectangular sub-pixel on opposite first and/or second sides of the rectangular sub-pixel and having a first side opposite to a long side and/or a width of the rectangular sub-pixel, and an orthographic projection of the non-rectangular sub-pixel on the first side is within the first side.