Abstract: The present disclosure provides a three-dimensional NAND memory device, comprising a NAND string including a memory cell to be inhibited to program, a word line driver, and a controller configured to control the word line driver to perform a programming operation on the memory cell controlled by a selected word line of a plurality of word lines including a first unselected word line adjacent to the selected word line, a first plurality of unselected word lines adjacent to the first unselected word line, and a second plurality of unselected word lines adjacent to the first plurality of unselected word lines. The programming operation includes applying a programming voltage signal to the selected word line; applying a first pass voltage to the first plurality of unselected word lines; and applying a second pass voltage to the second plurality of unselected word lines, the first pass voltage is different from the second pass voltage.

Abstract: A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.

Abstract: A selenium-chelating pea oligopeptide, a preparation method thereof and use thereof. After the selenium-chelating pea oligopeptide is subjected to digestion treatment in at least one of following three ways, a change rate of selenium content not more than 3% with respect to the selenium content before the digestion treatment: hydrolyzing for 4 hours by a pepsin at a pH value of 2 and a temperature of 37° C.; hydrolyzing for 6 hours by a trypsin at a pH value of 7.5 and a temperature of 37° C.; maintaining the temperature constant at 37° C., firstly hydrolyzing for 4 hours by the pepsin at a pH value of 2, and then continuing to hydrolyze for 6 hours by a trypsin at a pH value of 6.8. The preparation method thereof includes mixing and reacting an aqueous solution of pea oligopeptide and sodium selenite, and then being subjected to alcohol precipitation and drying.

Abstract: A display substrate, a manufacturing method therefor, and a display device. The display substrate includes: a base substrate; a light-emitting substrate disposed on the base substrate and the light-emitting substrate being configured to emit incident light; a color conversion layer disposed at a side of the light emitting substrate away from the base substrate and the color conversion layer being configured to convert the incident light emitted from the light emitting substrate into light of a specific color; a selective reflection layer disposed on a side of the color conversion layer away from the base substrate and the selective reflection layer being configured to reflect incident light not converted by the color conversion layer to the color conversion layer and to transmit light of the specific color converted by the color conversion layer.

Abstract: A memory device includes a first select line coupled to a first select transistor, a second select line coupled to a second select transistor, a word line coupled to a memory cell and located between the first select line and the second select line, and a peripheral circuit coupled to the first select line, the second select line, and the word line. The peripheral circuit is configured to apply a first voltage to the first select line to pre-program the first select transistor at a first time point in a first phase during an erasing operation. A voltage of the first select line at a second time point in a second phase after the first phase during the erasing operation is a second voltage greater than the first voltage. A voltage of the word line in the second phase during the erasing operation is a third voltage lower than the first voltage.

Abstract: Embodiments of the present disclosure disclose a method and apparatus for a scenario of editing multimedia resources, a device and a storage medium. The method includes: in response to an editing instruction triggered for a target editing template, displaying an import page of a material segment to be edited corresponding to the target editing template, wherein a setting entry for the material segment to be edited and a prompt entry for the material segment to be edited are presented on the import page; in response to a trigger for the prompt entry, displaying an original material segment corresponding to the material segment to be edited; in response to a trigger operation for the setting entry, determining the material segment to be edited; and editing the material segment to be edited into a target multimedia resource in a target editing mode indicated by the target editing template.

Abstract: According to one aspect, a method of operating a memory is provided. The method may include applying a first power supply voltage to a common source during a program precharge process. The method may include applying a first voltage to a first bottom gate line and applying a second voltage to a second bottom gate line starting at a first moment of the program precharge process. The method may include applying a second power supply voltage to the first bottom gate line and applying a third voltage to the second bottom gate line after the first moment of the program precharge process.

Abstract: The present disclosure provides a method for operating a memory, a memory and a memory system, and relates to the technical field of semiconductor chip. The method includes: during the erase phase, applying an erase voltage to the word line, and applying an erase voltage to the select line coupled to a target select gate; during the program phase for select gate, applying a pass voltage to the word line, and applying a program voltage to the select line coupled to the target select gate.

Abstract: An example method performed by a network node may include obtaining measurement information of interference cell(s) of at least one UE and/or traffic information of the interference cell(s); adjusting a target block error rate (BLER) for a target UE in the at least one UE according to the measurement information of the interference cell(s) and/or the traffic information of the interference cell(s); and transmitting data to the target UE based on the adjusted target BLER.

Abstract: This application discloses a method for analyzing a wafer angle in semiconductor integrated circuit manufacturing, including step 1: collecting machine angle data; step 2: predicting and forming an angle trajectory map of each analyzed wafer in a process according to the machine angle data; step 3: performing first grouping on defective wafers in an analyzed lot according to defect types; step 4: selecting one first group as a selected group, and performing second grouping on each defective wafer in the selected group according to defect directions; and step 5: calculating a direction difference between defect directions of second groups, and determining a site and a machine where a defect occurs in combination with the direction difference and an angle difference in the angle trajectory map of each detective wafer in the selected group. This application further discloses a system for analyzing a wafer angle in semiconductor integrated circuit manufacturing.

Abstract: The present disclosure provides a memory device, a memory system, and an operation method of a memory device, and relates to the technical field of semiconductor chips. The memory device includes a memory cell array including a source layer, a bottom select gate layer, and a gate layer, and the bottom select gate layer is located between the source layer and the gate layer, wherein the bottom select gate layer includes a plurality of bottom select gates, and a bottom select gate of a first memory string and a bottom select gate of a second memory string are connected with a same select line; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to apply a selection voltage to the select line to control the first memory string and the second memory string.

Abstract: A display substrate includes a base substrate, a plurality of first electrodes, a first pixel defining layer, and a second pixel defining layer disposed on the base substrate, and light-emitting layers disposed in a plurality of second opening regions. The first pixel defining layer includes a plurality of first opening regions, and each of the first opening regions exposes at least a portion of a first electrode. The second pixel defining layer includes the plurality of second opening regions, each second opening regions corresponds to at least two first opening regions, and the orthogonal projections of the at least two first opening regions on the base substrate are located within the orthogonal projection of the second opening region on the base substrate. The light-emitting layers overspreads the plurality of second opening regions in a plane perpendicular to a thickness direction of the base substrate, respectively.

Abstract: A memory device, a memory system, and a program operation method are disclosed. In one example, at an ith programming loop, in response to determining that index i is greater than or equal to a first preset value and less than an initial verification loop number corresponding to a target state of memory cells in the memory device, an ith programming inhibition operation may be performed on the memory cells of the target state. Index i may be a positive integer, and the initial verification loop number may indicate a programming loop number that starts a verification operation corresponding to the target state of the memory cells.

Abstract: A dust mite attractant, including 1-10 parts by weight of neryl propionate, 1-4 parts by weight of geranyl formate, 1-8 parts by weight of methyl eugenol, 1-8 parts by weight of geraniol and 1-6 parts by weight of a terpene. In the preparation process of a microcapsule of the dust mite attractant, an aqueous phase, an oil phase, and a tetraethylenepentamine solution are separately prepared. The aqueous phase is slowly added with the oil phase, and emulsified to obtain an emulsified mixture. The emulsified mixture is transferred to an oil bath, added dropwise with the tetraethylenepentamine solution and reacted at a constant temperature for 2.5 h to obtain the microcapsule.

Abstract: A memory device includes memory cells, word lines respectively coupled to the memory cells, bit lines respectively coupled to the memory cells, and a peripheral circuit coupled to the word lines and the bit lines. The peripheral circuit is configured to apply a first program voltage to a first word line of the word lines, after applying the first program voltage to the first word line, apply a second program voltage to a second word line of the word lines, and after applying the second program voltage to the second word line, perform a program pre-charge operation. To perform the pre-charge operation, a first voltage is applied to the second word line, a second voltage is applied to the first word line, and after the program pre-charge operation, a third program voltage is applied to the first word line. The first voltage is greater than the second voltage.

Abstract: A display base plate includes: a substrate (101), a first electrode layer (102) formed on the substrate (101), and a first pixel definition layer (103) and a second pixel definition layer (104) formed on the first electrode layer (102); the first pixel definition layer (103) divides the substrate (101) into a plurality of pixel regions (105), each pixel region (105) includes a plurality of subpixel regions (1050) distributed along a first direction, and two adjacent subpixel regions (1050) are separated by the second pixel definition layer (104); in the first direction, surfaces of each pixel region (105) in contact with the first pixel definition layer (103) include a plurality of first curved surfaces (1061) and a plurality of second curved surfaces (1062), and the first curved surfaces (1061) and the second curved surfaces (1062) are protruded away from the pixel region (105) to which they belong.

Abstract: A display substrate includes a base substrate, a thin film transistor array layer, a planarization layer, a first electrode and a pixel definition layer, the pixel definition layer defining a plurality of pixel openings, each pixel opening includes a first edge and a second edge adjacent to each other, the pixel definition layer includes a first pixel definition layer parallel to the first edge and a second pixel definition layer parallel to the second edge. A surface of the first pixel definition layer away from the base substrate is located at a level lower than a surface of the second pixel definition layer away from the base substrate, a groove parallel to the first edge is arranged in a surface of the planarization layer away from the base substrate, at least a part of the first pixel definition layer is arranged in the groove.

Abstract: The present disclosure provides a three-dimensional NAND memory device, comprising a memory array comprising blocks, each block includes first memory cells and second memory cells connected in series to a bit line, a word line driver, and a controller configured to control the word line driver to: performing a programming operation on a memory cell in the first memory cells, the memory cell is controlled by a selected word line of first word lines corresponding to the first memory cells, the first word lines comprising first unselected word lines adjacent to the selected word line, and the performing the programming operation comprises: applying a programming voltage signal to the selected word line to program the memory cell into a target state; applying a first pass voltage to the first unselected word lines; and applying a second pass voltage to second word lines corresponding to the second memory cells.

Abstract: A system and method for joint dynamic interest request forwarding and dynamic cache placement and eviction and provided within the context of the Named Data Networking (NDN) architecture. The system and method employ a virtual control plane that operates on the user demand rate for data objects in the network, and an actual plane that handles Interest Packets and Data Packets. Distributed algorithms within the virtual plane achieve network load balancing through dynamic forwarding and caching, thereby maximizing the user demand rate that the NDN network can satisfy. A method of congestion control is also provided to achieve optimal network fairness using the VIP framework.

Abstract: This disclosure relates to techniques for multi-RAT and DSDA capable wireless devices to handle frame blanking in a wireless communication system. A wireless device may establish wireless links according to a first radio access technology and a second radio access technology. The wireless device may determine to perform transmit and receive blanking for one or more antennas of the wireless device for the first radio access technology to perform sounding reference signal transmissions for the second radio access technology based at least in part on a band combination for the wireless links. The wireless device may determine a modification to channel state feedback reporting for the first radio access technology based at least in part on the transmit and receive blanking. The wireless device may perform channel state feedback reporting using the determined modification.