Abstract: An array substrate is provided, including: multiple columns of pixel units on a substrate, including multiple first and second pixel unit columns alternately in a row direction; each first/second pixel unit column includes multiple first/second pixel units in a column direction; first and second pixel units adjacent to each other are staggered in the row direction in adjacent first and second pixel unit columns. Each first/second pixel unit includes at least two sub-pixels of different colors in multiple columns, and each column of sub-pixels have a same color; each first/second pixel unit includes one rectangular sub-pixel and at least one non-rectangular sub-pixel on opposite first and/or second sides of the rectangular sub-pixel and having a first side opposite to a long side and/or a width of the rectangular sub-pixel, and an orthographic projection of the non-rectangular sub-pixel on the first side is within the first side.

Abstract: Provided are a display substrate and a display device. The display substrate includes a driving transistor and a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, the second electrode plate is arranged in a same layer as the channel of the driving transistor, the second electrode plate is closer to the base substrate than the first electrode plate, an orthographic projection of the second electrode plate on the base substrate overlaps with an orthographic projection of the pixel opening on the base substrate, the display substrate satisfies a following relationship: a value range of (W*L+S2)*M1/M2 is [0.014, 0.133], and a value range of S2/(W*L) is [2.82, 28.

Abstract: The present disclosure provides a three-dimensional NAND memory device, comprising a NAND string including a memory cell to be inhibited to program, a word line driver, and a controller configured to control the word line driver to perform a programming operation on the memory cell controlled by a selected word line of a plurality of word lines including a first unselected word line adjacent to the selected word line, a first plurality of unselected word lines adjacent to the first unselected word line, and a second plurality of unselected word lines adjacent to the first plurality of unselected word lines. The programming operation includes applying a programming voltage signal to the selected word line; applying a first pass voltage to the first plurality of unselected word lines; and applying a second pass voltage to the second plurality of unselected word lines, the first pass voltage is different from the second pass voltage.

Abstract: A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.

Abstract: A display substrate, a manufacturing method therefor, and a display device. The display substrate includes: a base substrate; a light-emitting substrate disposed on the base substrate and the light-emitting substrate being configured to emit incident light; a color conversion layer disposed at a side of the light emitting substrate away from the base substrate and the color conversion layer being configured to convert the incident light emitted from the light emitting substrate into light of a specific color; a selective reflection layer disposed on a side of the color conversion layer away from the base substrate and the selective reflection layer being configured to reflect incident light not converted by the color conversion layer to the color conversion layer and to transmit light of the specific color converted by the color conversion layer.

Abstract: A memory device includes a first select line coupled to a first select transistor, a second select line coupled to a second select transistor, a word line coupled to a memory cell and located between the first select line and the second select line, and a peripheral circuit coupled to the first select line, the second select line, and the word line. The peripheral circuit is configured to apply a first voltage to the first select line to pre-program the first select transistor at a first time point in a first phase during an erasing operation. A voltage of the first select line at a second time point in a second phase after the first phase during the erasing operation is a second voltage greater than the first voltage. A voltage of the word line in the second phase during the erasing operation is a third voltage lower than the first voltage.

Abstract: According to one aspect, a method of operating a memory is provided. The method may include applying a first power supply voltage to a common source during a program precharge process. The method may include applying a first voltage to a first bottom gate line and applying a second voltage to a second bottom gate line starting at a first moment of the program precharge process. The method may include applying a second power supply voltage to the first bottom gate line and applying a third voltage to the second bottom gate line after the first moment of the program precharge process.

Abstract: The present disclosure provides a memory device, a memory system, and an operation method of a memory device, and relates to the technical field of semiconductor chips. The memory device includes a memory cell array including a source layer, a bottom select gate layer, and a gate layer, and the bottom select gate layer is located between the source layer and the gate layer, wherein the bottom select gate layer includes a plurality of bottom select gates, and a bottom select gate of a first memory string and a bottom select gate of a second memory string are connected with a same select line; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to apply a selection voltage to the select line to control the first memory string and the second memory string.

Abstract: The present disclosure provides a method for operating a memory, a memory and a memory system, and relates to the technical field of semiconductor chip. The method includes: during the erase phase, applying an erase voltage to the word line, and applying an erase voltage to the select line coupled to a target select gate; during the program phase for select gate, applying a pass voltage to the word line, and applying a program voltage to the select line coupled to the target select gate.

Abstract: This application discloses a method for analyzing a wafer angle in semiconductor integrated circuit manufacturing, including step 1: collecting machine angle data; step 2: predicting and forming an angle trajectory map of each analyzed wafer in a process according to the machine angle data; step 3: performing first grouping on defective wafers in an analyzed lot according to defect types; step 4: selecting one first group as a selected group, and performing second grouping on each defective wafer in the selected group according to defect directions; and step 5: calculating a direction difference between defect directions of second groups, and determining a site and a machine where a defect occurs in combination with the direction difference and an angle difference in the angle trajectory map of each detective wafer in the selected group. This application further discloses a system for analyzing a wafer angle in semiconductor integrated circuit manufacturing.

Abstract: A memory device, a memory system, and a program operation method are disclosed. In one example, at an ith programming loop, in response to determining that index i is greater than or equal to a first preset value and less than an initial verification loop number corresponding to a target state of memory cells in the memory device, an ith programming inhibition operation may be performed on the memory cells of the target state. Index i may be a positive integer, and the initial verification loop number may indicate a programming loop number that starts a verification operation corresponding to the target state of the memory cells.

Abstract: A display substrate includes a base substrate, a plurality of first electrodes, a first pixel defining layer, and a second pixel defining layer disposed on the base substrate, and light-emitting layers disposed in a plurality of second opening regions. The first pixel defining layer includes a plurality of first opening regions, and each of the first opening regions exposes at least a portion of a first electrode. The second pixel defining layer includes the plurality of second opening regions, each second opening regions corresponds to at least two first opening regions, and the orthogonal projections of the at least two first opening regions on the base substrate are located within the orthogonal projection of the second opening region on the base substrate. The light-emitting layers overspreads the plurality of second opening regions in a plane perpendicular to a thickness direction of the base substrate, respectively.

Abstract: A memory device includes memory cells, word lines respectively coupled to the memory cells, bit lines respectively coupled to the memory cells, and a peripheral circuit coupled to the word lines and the bit lines. The peripheral circuit is configured to apply a first program voltage to a first word line of the word lines, after applying the first program voltage to the first word line, apply a second program voltage to a second word line of the word lines, and after applying the second program voltage to the second word line, perform a program pre-charge operation. To perform the pre-charge operation, a first voltage is applied to the second word line, a second voltage is applied to the first word line, and after the program pre-charge operation, a third program voltage is applied to the first word line. The first voltage is greater than the second voltage.

Abstract: A display substrate includes a base substrate, a thin film transistor array layer, a planarization layer, a first electrode and a pixel definition layer, the pixel definition layer defining a plurality of pixel openings, each pixel opening includes a first edge and a second edge adjacent to each other, the pixel definition layer includes a first pixel definition layer parallel to the first edge and a second pixel definition layer parallel to the second edge. A surface of the first pixel definition layer away from the base substrate is located at a level lower than a surface of the second pixel definition layer away from the base substrate, a groove parallel to the first edge is arranged in a surface of the planarization layer away from the base substrate, at least a part of the first pixel definition layer is arranged in the groove.

Abstract: A display base plate includes: a substrate (101), a first electrode layer (102) formed on the substrate (101), and a first pixel definition layer (103) and a second pixel definition layer (104) formed on the first electrode layer (102); the first pixel definition layer (103) divides the substrate (101) into a plurality of pixel regions (105), each pixel region (105) includes a plurality of subpixel regions (1050) distributed along a first direction, and two adjacent subpixel regions (1050) are separated by the second pixel definition layer (104); in the first direction, surfaces of each pixel region (105) in contact with the first pixel definition layer (103) include a plurality of first curved surfaces (1061) and a plurality of second curved surfaces (1062), and the first curved surfaces (1061) and the second curved surfaces (1062) are protruded away from the pixel region (105) to which they belong.

Abstract: The present disclosure provides a three-dimensional NAND memory device, comprising a memory array comprising blocks, each block includes first memory cells and second memory cells connected in series to a bit line, a word line driver, and a controller configured to control the word line driver to: performing a programming operation on a memory cell in the first memory cells, the memory cell is controlled by a selected word line of first word lines corresponding to the first memory cells, the first word lines comprising first unselected word lines adjacent to the selected word line, and the performing the programming operation comprises: applying a programming voltage signal to the selected word line to program the memory cell into a target state; applying a first pass voltage to the first unselected word lines; and applying a second pass voltage to second word lines corresponding to the second memory cells.

Abstract: A system and method for joint dynamic interest request forwarding and dynamic cache placement and eviction and provided within the context of the Named Data Networking (NDN) architecture. The system and method employ a virtual control plane that operates on the user demand rate for data objects in the network, and an actual plane that handles Interest Packets and Data Packets. Distributed algorithms within the virtual plane achieve network load balancing through dynamic forwarding and caching, thereby maximizing the user demand rate that the NDN network can satisfy. A method of congestion control is also provided to achieve optimal network fairness using the VIP framework.

Abstract: A display base plate includes sub-pixels, substrate, pixel defining layer disposed on side of substrate which includes first, second and third retaining wall; first and second retaining wall configured to form opening area of sub-pixel, first retaining wall is located between opening areas of adjacent sub-pixels having different colors, second retaining wall is located between opening areas of adjacent sub-pixels having same color; third retaining wall is disposed at side of first retaining wall facing away from substrate, and orthographic projection of third retaining wall on substrate is located within range of orthographic projection of first retaining wall on substrate; surface of side of first retaining wall away from substrate is higher than surface of side of second retaining wall away from substrate, and is lower than a surface of side third retaining wall away from substrate.

Abstract: A memory device, an operating method thereof, a system, and a non-transitory tangible storage medium are disclosed. The memory device includes a source line (SL), a bit line (BL), a memory string, a word line, a select line and a peripheral circuit. The memory string includes a memory cell and a select transistor including a storage layer. The word line is coupled to the memory cell. The select line is coupled to the select transistor. The peripheral circuit is coupled to the SL, the BL, the select line, and the word line. The peripheral circuit is configured to: apply a first voltage to the select line; and apply a second voltage to the SL and/or the BL, in which a first peak level of the first voltage is greater than a second peak level of second voltage.

Abstract: A memory device includes memory cells in rows, word lines respectively coupled to the rows, and a control circuitry coupled to the memory cells via the word lines. The control circuitry is configured to apply a first program voltage to a first word line of the word lines. The first word line is coupled to a first row of the memory cells. The control circuitry is also configured to, after applying the first program voltage to the first word line, apply a second program voltage to a second word line of the word lines. The second word line is coupled to a second row of the memory cells. The control circuitry is also configured to, after applying the second program voltage to the second word line, apply a first pre-charge voltage to the first word line and a second pre-charge voltage to the second word line. The second pre-charge voltage is greater than the first pre-charge voltage.