Abstract: A system and method for joint dynamic interest request forwarding and dynamic cache placement and eviction and provided within the context of the Named Data Networking (NDN) architecture. The system and method employ a virtual control plane that operates on the user demand rate for data objects in the network, and an actual plane that handles Interest Packets and Data Packets. Distributed algorithms within the virtual plane achieve network load balancing through dynamic forwarding and caching, thereby maximizing the user demand rate that the NDN network can satisfy. A method of congestion control is also provided to achieve optimal network fairness using the VIP framework.

Abstract: Provided is a display panel, including: a substrate; a pixel definition layer having at least one strip-shaped first opening therein, wherein the first opening includes an expansion region and a contraction region that are alternately arranged along a first direction, and a size of the expansion region in a second direction is larger than a size of the expansion region in the second direction; a plurality of first partition walls, disposed in the first opening, wherein each of the first partition walls extends along the second direction, and two ends of the first partition wall are respectively in contact with two side walls of the first opening to partition the first opening into a plurality of pixel openings; and a plurality of light-emitting portions, respectively disposed in the plurality of pixel openings; wherein a height of the first partition wall is less than a height of the pixel definition layer.

Abstract: Provided are an array substrate and a manufacturing method thereof, and a display device.

Abstract: Provided in the present disclosure are a display panel and a manufacturing method therefor, and a display apparatus. A pixel defining layer includes a plurality of first barrier walls and a plurality of second barrier walls, which are arranged in an intersecting manner, where a height of the first barrier wall is smaller than a height of the second barrier wall, and orthographic projections of via holes for connecting light emitting devices on a base substrate are located in orthographic projections of the second barrier walls on the base substrate. Due to a great thickness of the second barrier walls, an effect of covering via holes can be better by providing the via holes below the second barrier walls.

Abstract: Disclosed is an OLED display panel including a display region, a packaging region and a cutting region disposed. The packaging region is provided with a plurality of modification stripes and includes a first region and a second region. The modification stripes include lyophilic stripes and lyophobic stripes disposed at intervals, and any two adjacent modification stripes include one lyophilic stripe and one lyophobic stripe. In the first region: width ranges of the lyophilic stripes and the lyophobic stripes are both 1-100 nm; and in the second region: a width range of the lyophilic stripes is 1-100 nm, a width range of the lyophobic stripes is 200-1000 nm, and a width of the lyophobic stripes in the second region gradually increases in a direction from the display region to the cutting region.

Abstract: A method of fabricating vertical cavity surface emitting laser, comprising: providing a first substrate formed with a dielectric DBR and a first bonding layer, and a second substrate formed with a etch-stop layer, a heavily doped layer, an active region, a current-confinement layer, and an arsenide DBR firstly, then sticking a third substrate on the arsenide DBR, then removing the second substrate and the etch-stop layer, next bonding the heavily doped layer to the dielectric DBR, next removing the third substrate, finally forming a p-type electrode contact and an n-type electrode contact.

Abstract: The present disclosure provides a three-dimensional NAND memory device, comprising a NAND string including a memory cell to be inhibited to program, a word line driver, and a controller configured to control the word line driver to perform a programming operation on the memory cell controlled by a selected word line of a plurality of word lines including a first unselected word line adjacent to the selected word line, a first plurality of unselected word lines adjacent to the first unselected word line, and a second plurality of unselected word lines adjacent to the first plurality of unselected word lines. The programming operation includes applying a programming voltage signal to the selected word line; applying a first pass voltage to the first plurality of unselected word lines; and applying a second pass voltage to the second plurality of unselected word lines, the first pass voltage is different from the second pass voltage.

Abstract: An array substrate includes a base and a pixel defining layer and light-emitting layers that are disposed on the base. The pixel defining layer includes defining strips extending in a first direction and defining portions extending in a second direction, the defining strips and the defining portions define openings, defining portions located between two adjacent defining strips are spaced apart in the first direction, a defining portion includes at least two second sub-portions and first sub-portion(s) connected to the two adjacent defining strips through the at least two second sub-portions, thickness of a defining strip is greater than a thickness of a first sub-portion, and the thickness of the first sub-portion is greater than a thickness of a second sub-portion. Portion(s) of a light-emitting layer is disposed in a corresponding opening, and at least two light-emitting layers between the two adjacent defining strips are connected to form a one-piece structure.

Abstract: A memory device includes a first deck including a first set of word lines, a second deck including a second set of word lines, and a controller. The controller is configured to apply a program voltage to a first word line of the first set of word lines, apply a first pass voltage to a second word line of the second set of word lines while applying the program voltage to the first word line, and apply a second pass voltage to a third word line of the first set of word lines while applying the program voltage to the first word line. The third word line is between the first word line and the second word line. The second pass voltage is greater than the first pass voltage.

Abstract: An array substrate, including: a plurality of first pixel defining portions and a plurality of second pixel defining portions arranged on a base substrate and jointly define a plurality of pixel openings; and a light emitting functional layer arranged on the base substrate and includes a first light emitting portion and a second light emitting portion that emit different colors of light, at least a part of the first light emitting portion and the second light emitting portion is respectively located in a first pixel opening and a second pixel opening. An orthographic projection of a combination of two adjacent pixel openings separated by the second pixel defining portion on a base substrate has a first size in a first direction and a second size in a second direction, and a ratio of the first size to the second size is within a range of 0.8 to 1.2.

Abstract: A non-volatile memory device includes a memory string, a select gate line coupled to the memory string, word lines coupled to the memory string and including a selected word line, and a control circuit coupled to the select gate line and the word lines, and configured to apply word line pre-pulse signals to at least two groups of the word lines disposed between the select gate line and the selected word line during a pre-charge period. The at least two groups of the word lines include a first group and a second group disposed between the first group and the select gate line. A voltage level of a second word line pre-pulse signal applied to the second group is greater than a voltage level of a first word line pre-pulse signal applied to the first group. A voltage level of at least one word line pre-pulse signal of the word line pre-pulse signals is greater than 0.

Abstract: A memory device, an operating method thereof, a system, and a non-transitory tangible storage medium are disclosed. The memory device includes a source line (SL), a bit line (BL), a memory string, a word line, a select line and a peripheral circuit. The memory string includes a memory cell and a select transistor including a storage layer. The word line is coupled to the memory cell. The select line is coupled to the select transistor. The peripheral circuit is coupled to the SL, the BL, the select line, and the word line. The peripheral circuit is configured to: apply a first voltage to the select line; and apply a second voltage to the SL and/or the BL, in which a first peak level of the first voltage is greater than a second peak level of second voltage.

Abstract: A method for operating a memory device is disclosed. The memory device includes a first word line, a second word line, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first word line and the second word line. A first pass voltage is applied to the first dummy word line in a program operation. A second pass voltage is applied to the second dummy word line in the program operation. The first pass voltage is different from the second pass voltage.

Abstract: A thermal interface comprising a polymer composite comprising a polymer and a self-assembled boron arsenide.

Abstract: A memory device may include a first set of word lines in a first zone and a second set of word lines in a second zone. When programming memory cells coupled to a first target word line of the first set of word lines, a first pass voltage may be applied to at least one word line of the first set of word lines. When programming memory cells coupled to a second target word line of the second set of word lines, a second pass voltage may be applied to at least one word line of the second set of word lines. The at least one word line of the first set of word lines and the at least one word line of the second set of word lines have been programmed. The second pass voltage may be higher than the first pass voltage.

Abstract: A non-volatile memory device includes a plurality of word lines and a control circuit. The control circuit is configured to apply a first word line pre-pulse signal of a plurality of word line pre-pulse signals to a first group of the plurality of word lines, apply a second word line pre-pulse signal of the plurality of word line pre-pulse signals to a second group of the plurality of word lines during a pre-charge period, and apply a third word line pre-pulse signal of the plurality of word lines pre-pulse signals to a third group of the plurality of word lines during the pre-charge period. A voltage level of the second word line pre-pulse signal is greater than that of the first word line pre-pulse signal, and a voltage level of the third word line pre-pulse signal is greater than that of the second word line pre-pulse signal.

Abstract: The present disclosure provides a display substrate, a method for preparing the same, and a display device. The display substrate includes an insulating pattern whose surface layer is composed of a hydrophobic fluorine-containing material, so the organic ink used to prepare a light emitting layer does not overflow outside a pixel area. The method for preparing the display substrate includes: forming a rheological insulating material layer on the base substrate; curing the rheological insulating material layer, and patterning the cured insulating material layer to obtain an insulating pattern; heating the insulating pattern, to gather the hydrophobic insulating structure on a surface of the insulating pattern away from the base substrate; heating the gathered hydrophobic insulating structure to melt it, and then cooling the molten hydrophobic insulating structure to form a metal pattern on the surface of the insulating pattern.

Abstract: A method for operating a memory is disclosed. The memory includes a first group of word lines, a second group of word lines, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first group of word lines and the second group of word lines. A first pass voltage is applied to the first dummy word line and applying a second pass voltage to the second dummy word line. A program voltage is applied to a selected word line, wherein a condition is met: a first voltage difference between the first pass voltage and a first threshold voltage of a first dummy cell corresponding to the first dummy word line is different from a second voltage difference between the second pass voltage and a second threshold voltage of a second dummy cell corresponding to the second dummy word line.

Abstract: A memory device, a memory system, and a program operation method are disclosed. In one example, at an ith programming loop, in response to determining that index i is greater than or equal to a first preset value and less than an initial verification loop number corresponding to a target state of memory cells in the memory device, an ith programming inhibition operation may be performed on the memory cells of the target state. Index i may be a positive integer, and the initial verification loop number may indicate a programming loop number that starts a verification operation corresponding to the target state of the memory cells.

Abstract: Provided are a display substrate, a preparation method thereof and a display apparatus. The display substrate includes a substrate, a drive circuit layer disposed on the substrate and a light emitting structure layer disposed on a side of the drive circuit layer away from the substrate, wherein the drive circuit layer includes a transistor, and the light emitting structure layer includes a first electrode, a pixel define layer, an organic light emitting layer and a second electrode, wherein the first electrode is connected with a drain electrode of the transistor, and the organic light emitting layer is located between the first electrode and the second electrode; the pixel define layer includes a plurality of first retaining walls and a plurality of second retaining walls.