Abstract: The present disclosure provides a display substrate, a method for preparing the same, and a display device. The display substrate includes an insulating pattern whose surface layer is composed of a hydrophobic fluorine-containing material, so the organic ink used to prepare a light emitting layer does not overflow outside a pixel area. The method for preparing the display substrate includes: forming a rheological insulating material layer on the base substrate; curing the rheological insulating material layer, and patterning the cured insulating material layer to obtain an insulating pattern; heating the insulating pattern, to gather the hydrophobic insulating structure on a surface of the insulating pattern away from the base substrate; heating the gathered hydrophobic insulating structure to melt it, and then cooling the molten hydrophobic insulating structure to form a metal pattern on the surface of the insulating pattern.

Abstract: A method for operating a memory is disclosed. The memory includes a first group of word lines, a second group of word lines, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first group of word lines and the second group of word lines. A first pass voltage is applied to the first dummy word line and applying a second pass voltage to the second dummy word line. A program voltage is applied to a selected word line, wherein a condition is met: a first voltage difference between the first pass voltage and a first threshold voltage of a first dummy cell corresponding to the first dummy word line is different from a second voltage difference between the second pass voltage and a second threshold voltage of a second dummy cell corresponding to the second dummy word line.

Abstract: A memory device, a memory system, and a program operation method are disclosed. In one example, at an ith programming loop, in response to determining that index i is greater than or equal to a first preset value and less than an initial verification loop number corresponding to a target state of memory cells in the memory device, an ith programming inhibition operation may be performed on the memory cells of the target state. Index i may be a positive integer, and the initial verification loop number may indicate a programming loop number that starts a verification operation corresponding to the target state of the memory cells.

Abstract: Provided are a display substrate, a preparation method thereof and a display apparatus. The display substrate includes a substrate, a drive circuit layer disposed on the substrate and a light emitting structure layer disposed on a side of the drive circuit layer away from the substrate, wherein the drive circuit layer includes a transistor, and the light emitting structure layer includes a first electrode, a pixel define layer, an organic light emitting layer and a second electrode, wherein the first electrode is connected with a drain electrode of the transistor, and the organic light emitting layer is located between the first electrode and the second electrode; the pixel define layer includes a plurality of first retaining walls and a plurality of second retaining walls.

Abstract: A memory device includes memory cells in rows, word lines respectively coupled to the rows, and a control circuitry coupled to the memory cells via the word lines. The control circuitry is configured to apply a first program voltage to a first word line of the word lines. The first word line is coupled to a first row of the memory cells. The control circuitry is also configured to, after applying the first program voltage to the first word line, apply a second program voltage to a second word line of the word lines. The second word line is coupled to a second row of the memory cells. The control circuitry is also configured to, after applying the second program voltage to the second word line, apply a first pre-charge voltage to the first word line and a second pre-charge voltage to the second word line. The second pre-charge voltage is greater than the first pre-charge voltage.

Abstract: In some aspects, a memory device is provided. The memory device includes a plurality of memory strings and a peripheral circuit. One of the memory strings includes memory cells, a select transistor coupled to a select line and a bit line, and a dummy cell coupled to a dummy word line and arranged between the select transistor and the memory cells. The peripheral circuit is coupled to the memory strings and configured to, in a pre-pulse period of a program operation, maintain a first voltage on the select line to retain an on-state of the select transistor and apply a second voltage to the dummy word line to turn off the dummy cell. After applying the second voltage to the dummy word line, the peripheral circuit is further configured to apply a third voltage to the select line to turn off the select transistor.

Abstract: A memory device includes memory cells in rows, word lines respectively coupled to the rows, and a control circuitry coupled to the memory cells via the word lines. The control circuitry is configured to apply a first program voltage to a first word line of the word lines. The first word line is coupled to a first row of the memory cells. The control circuitry is also configured to, after applying the first program voltage to the first word line, apply a second program voltage to a second word line of the word lines. The second word line is coupled to a second row of the memory cells. The control circuitry is also configured to, after applying the second program voltage to the second word line, apply a first pre-charge voltage to the first word line and a second pre-charge voltage to the second word line. The second pre-charge voltage is greater than the first pre-charge voltage.

Abstract: A method for operating a memory is disclosed. The memory includes a first group of word lines, a second group of word lines, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first group of word lines and the second group of word lines. A first pass voltage is applied to the first dummy word line and applying a second pass voltage to the second dummy word line. A program voltage is applied to a selected word line, wherein a condition is met: a first voltage difference between the first pass voltage and a first threshold voltage of a first dummy cell corresponding to the first dummy word line is different from a second voltage difference between the second pass voltage and a second threshold voltage of a second dummy cell corresponding to the second dummy word line.

Abstract: Provided is a method for feature extraction of a remote sensing image based on tensor collaborative graph discriminant analysis, including: taking each of pixels as a center for intercepting a three-dimensional tensor data block; dividing experimental data into a training set and a test set in proportion; computing a Euclidean distance between a current training pixel and each class of training data; configuring a L2 norm collaborative representation model with a weight constraint; acquiring a projection matrix of each dimension of each of the three-dimensional tensor data block; and utilizing a low-dimensional projection matrix to obtain a training set and a test set, expanding the training set and the test set into a form of column vectors according to a feature dimension, inputting extracted low-dimensional features into a support vector machine classifier for classification, to determine a class of the test set, and evaluating, by a classification effect, performance of feature extraction.

Abstract: Provided is a method of manufacturing fiber with aligned porous structure, an apparatus, and applications of the fiber. The apparatus comprises: a fiber extrusion unit, a freezing unit, and a collection unit for collecting the frozen fibers, wherein fibers extruded from the fiber extrusion unit pass through the freezing unit. Continuous and large scale preparation of such fiber with aligned porous structure is achieved by combining directional freezing and solution spinning.

Abstract: Embodiments of the present application provide a display substrate comprising a plurality of first banks distributed in a first direction and a plurality of second banks distributed in a second direction. Two adjacent first banks define a group of sub-pixel units of the display substrate, and two adjacent second banks define one sub-pixel unit. The first bank has a height greater than a height of the second bank. Embodiments of the present application also disclose a manufacturing method of a display substrate and a display device.

Abstract: A memory device includes bit lines, and a cell array including strings, each of which includes memory cells, a select cell coupled to a respective one of the bit lines, and a dummy cell between the select cell and the memory cells. The memory device also includes a select line coupled to the select cells, a dummy word line coupled to the dummy cells, word lines each coupled to a respective row of the memory cells, and a controller coupled to the cell array. The controller is configured to drive a voltage on the dummy word line from a first level to a second level lower than the first level. The controller is also configured to drive a voltage on the select line from the first level to the second level, such that the voltage on the select line reaches the second level after the voltage on the dummy word line reaches the second level.

Abstract: Provided is a method for feature extraction of a hyperspectral images based on unsupervised latent low-rank projection learning, including: dividing hyperspectral images data into a training set and a test set in proportion; configuring a robust weight function, constructing a spectral constraint matrix according to the training set, and constructing a graph regularization constraint according to a locality preserving projection rule; approximately decompose row representation coefficients of a latent low-rank representation model, constructing a latent low-rank projection learning model in combination with the spectral constraint matrix and the graph regularization constraint; optimizing and solving the latent low-rank projection learning model; and outputting classes of all samples in the test set, and taking low-dimensional features of the training set as training samples of a support vector machine, to classify low-dimensional features of the test set, and evaluating, by the quality of classification resu

Abstract: A transparent display panel includes a base, a first pixel defining structure and a first light-emitting devices. The first pixel defining structure is disposed on the base and includes a first opening that has a light transmission region and a light-emitting region. The first light-emitting device is disposed on the base and includes an opaque electrode and a light-emitting functional layer. At least part of the opaque electrode is exposed by the first opening, and an orthographic projection of the opaque electrode does not overlap with the light transmission region. The light-emitting functional layer is disposed in the first opening and defined by the first opening. The orthographic projection of the opaque electrode and an orthographic projection of the light-emitting functional layer have an overlapping region, and at least a portion of the overlapping region is within the light-emitting region.

Abstract: A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.

Abstract: The embodiment of the present application provides an array substrate, display panel and display device.

Abstract: A memory includes a first deck including a first set of word lines, a second deck above the first deck and including a second set of word lines, and a controller. The controller is configured to apply a program voltage to a first target word line of the first set of word lines in the first deck, and apply a first pass voltage to at least one of the first set of word lines that is below the first target word line when applying the program voltage to the first target word line. The controller is also configured to apply the program voltage to a second target word line of the second set of word lines in the second deck, and apply a second pass voltage to at least one of the second set of word lines that is below the second target word line when applying the program voltage to the second target word line. The second pass voltage is greater than the first pass voltage.

Abstract: A probiotic composition for treating rapid eye movement sleep behavior disorder, is prepared from Bacillus licheniformis, Bifidobacterium longum, Lactobacillus acidophilus, Enterococcus faecalis, and pharmaceutically acceptable adjuvants. The probiotic composition can improve the symptoms of rapid eye movement sleep behavior disorder of a patient, improve RBD symptoms of idiopathic RBD patients and PD patients, improve the motor symptoms and reduce the daily levodopa equivalent dose in PD patients.

Abstract: A non-volatile memory device includes a plurality of word lines and a control circuit. The control circuit is configured to apply a first word line pre-pulse signal of a plurality of word line pre-pulse signals to a first group of the plurality of word lines, apply a second word line pre-pulse signal of the plurality of word line pre-pulse signals to a second group of the plurality of word lines during a pre-charge period, and apply a third word line pre-pulse signal of the plurality of word lines pre-pulse signals to a third group of the plurality of word lines during the pre-charge period. A voltage level of the second word line pre-pulse signal is greater than that of the first word line pre-pulse signal, and a voltage level of the third word line pre-pulse signal is greater than that of the second word line pre-pulse signal.

Abstract: A memory includes a first portion, a second portion and a controller. The first portion includes a first word line to a kth word line. The second portion is formed above the first portion and includes a (k+1)th word line to an mth word line. When an xth word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to an (x?2)th word line, a second voltage to an (x?1)th word line, and a third voltage to an (x+1)th word line. x, k and m are positive integers.