Abstract: A display substrate includes a base substrate, a thin film transistor array layer, a planarization layer, a first electrode and a pixel definition layer, the pixel definition layer defining a plurality of pixel openings, each pixel opening includes a first edge and a second edge adjacent to each other, the pixel definition layer includes a first pixel definition layer parallel to the first edge and a second pixel definition layer parallel to the second edge. A surface of the first pixel definition layer away from the base substrate is located at a level lower than a surface of the second pixel definition layer away from the base substrate, a groove parallel to the first edge is arranged in a surface of the planarization layer away from the base substrate, at least a part of the first pixel definition layer is arranged in the groove.

Abstract: A non-volatile memory device and a control method are provided e disclosed. The non-volatile memory device includes a memory array, a bit line, a plurality of word lines, a first control circuit, and second control circuit. The bit line is connected to a first memory string of the memory array. The plurality of word lines are connected to memory cells of the first memory string and each word line is connected to a respective memory cell. The first control circuit is configured to apply a bit line pre-pulse signal to the bit line during a pre-charge period. The second control circuit is configured to apply a word line signal to a selected word line and apply a plurality of word line pre-pulse signals to word lines disposed between a select gate line and the selected word line. Voltage levels of the plurality of word line pre-pulse signals are incremental.

Abstract: A display base plate and a manufacturing method therefor, a display panel and a display apparatus, relates to the technical field of display.

Abstract: The present disclosure provides a transparent display panel and method for manufacturing the same and a display device. The transparent display panel includes pixel units arranged in an array, and the pixel unit includes a light-emitting area and a transparent area. The pixel unit includes a pixel defining layer disposed in the light-emitting area and defining a plurality of opening areas. A light-emitting device is disposed in the opening area. The pixel unit further includes a transparent film layer disposed in the transparent area and being of a hydrophobic material. The transparent film layer includes a groove and an inclined channel, and the channel connects the groove with any one of the opening areas. A bottom surface of the groove is higher than a bottom surface of the opening area, and an area of the groove is greater than that of the opening area connected with the channel.

Abstract: An array substrate is provided, including: multiple columns of pixel units on a substrate, including multiple first and second pixel unit columns alternately in a row direction; each first/second pixel unit column includes multiple first/second pixel units in a column direction; first and second pixel units adjacent to each other are staggered in the row direction in adjacent first and second pixel unit columns. Each first/second pixel unit includes at least two sub-pixels of different colors in multiple columns, and each column of sub-pixels have a same color; each first/second pixel unit includes one rectangular sub-pixel and at least one non-rectangular sub-pixel on opposite first and/or second sides of the rectangular sub-pixel and having a first side opposite to a long side and/or a width of the rectangular sub-pixel, and an orthographic projection of the non-rectangular sub-pixel on the first side is within the first side.

Abstract: Disclosed is an OLED display panel including a display region, a packaging region and a cutting region disposed. The packaging region is provided with a plurality of modification stripes and includes a first region and a second region. The modification stripes include lyophilic stripes and lyophobic stripes disposed at intervals, and any two adjacent modification stripes include one lyophilic stripe and one lyophobic stripe. In the first region: width ranges of the lyophilic stripes and the lyophobic stripes are both 1-100 nm; and in the second region: a width range of the lyophilic stripes is 1-100 nm, a width range of the lyophobic stripes is 200-1000 nm, and a width of the lyophobic stripes in the second region gradually increases in a direction from the display region to the cutting region.

Abstract: An array substrate, including: a plurality of first pixel defining portions and a plurality of second pixel defining portions arranged on a base substrate and jointly define a plurality of pixel openings; and a light emitting functional layer arranged on the base substrate and includes a first light emitting portion and a second light emitting portion that emit different colors of light, at least a part of the first light emitting portion and the second light emitting portion is respectively located in a first pixel opening and a second pixel opening. An orthographic projection of a combination of two adjacent pixel openings separated by the second pixel defining portion on a base substrate has a first size in a first direction and a second size in a second direction, and a ratio of the first size to the second size is within a range of 0.8 to 1.2.

Abstract: Disclosed are an array substrate, a preparation method, a display panel, and a display device. A pixel limiting layer includes a first limiting sublayer and a second limiting sublayer which contact each other, and a first height of the first limiting sublayer in a direction perpendicular to a plane where a base substrate is located is greater than a second height of the second limiting sublayer in the direction perpendicular to the plane where the base substrate is located. Thus, when light emitting layers are formed in pixel openings by an ink jet printing process, light emitting layers having different colors can be spaced apart by the first limiting sublayer.

Abstract: Embodiments of the present application provide a display substrate comprising a plurality of first banks distributed in a first direction and a plurality of second banks distributed in a second direction. Two adjacent first banks define a group of sub-pixel units of the display substrate, and two adjacent second banks define one sub-pixel unit. The first bank has a height greater than a height of the second bank. Embodiments of the present application also disclose a manufacturing method of a display substrate and a display device.

Abstract: A display substrate includes a base substrate, a plurality of first electrodes, a first pixel defining layer, and a second pixel defining layer disposed on the base substrate, and light-emitting layers disposed in a plurality of second opening regions. The first pixel defining layer includes a plurality of first opening regions, and each of the first opening regions exposes at least a portion of a first electrode. The second pixel defining layer includes the plurality of second opening regions, each second opening regions corresponds to at least two first opening regions, and the orthogonal projections of the at least two first opening regions on the base substrate are located within the orthogonal projection of the second opening region on the base substrate. The light-emitting layers overspreads the plurality of second opening regions in a plane perpendicular to a thickness direction of the base substrate, respectively.

Abstract: A display substrate includes a substrate; a first pixel defining layer on the substrate, wherein the first pixel defining layer has a first container portion therein; a planarization pattern filled in the first container portion, wherein a surface of the planarization pattern distal to the substrate is flush with a surface of the first pixel defining layer distal to the substrate; a second pixel defining layer on a side of the planarization pattern distal to the substrate, wherein a second container portion is in the second pixel defining layer and penetrates through the second pixel defining layer along a stacking direction of the first pixel defining layer and the substrate, and an orthographic projection of the second container portion on the substrate falls within an orthographic projection of the first container portion on the substrate; and an organic functional layer in the second container portion.

Abstract: The present disclosure provides an array substrate, including: a base substrate; a planarization layer formed on the base substrate; a plurality of pixel electrodes formed on the planarization layer; and a pixel definition layer including a first pixel definition layer and a second pixel definition layer, the first pixel definition layer covering a periphery of each pixel electrode and exposing a central area of each pixel electrode, the second pixel definition layer being formed on the planarization layer between adjacent pixel electrodes and having a plurality of openings defining each sub-pixel unit; a bottom of a dam portion of the second pixel definition layer and a bottom of a dam portion of the first pixel definition layer adjacent thereto are separated by a predetermined distance, and a thickness of the second pixel definition layer is greater than a thickness of the first pixel definition layer.

Abstract: An array substrate includes a base and a pixel defining layer and light-emitting layers that are disposed on the base. The pixel defining layer includes defining strips extending in a first direction and defining portions extending in a second direction, the defining strips and the defining portions define openings, defining portions located between two adjacent defining strips are spaced apart in the first direction, a defining portion includes at least two second sub-portions and first sub-portion(s) connected to the two adjacent defining strips through the at least two second sub-portions, thickness of a defining strip is greater than a thickness of a first sub-portion, and the thickness of the first sub-portion is greater than a thickness of a second sub-portion. Portion(s) of a light-emitting layer is disposed in a corresponding opening, and at least two light-emitting layers between the two adjacent defining strips are connected to form a one-piece structure.

Abstract: A memory device includes bit lines, and a cell array including strings, each of which includes memory cells, a select cell coupled to a respective one of the bit lines, and a dummy cell between the select cell and the memory cells. The memory device also includes a select line coupled to the select cells, a dummy word line coupled to the dummy cells, word lines each coupled to a respective row of the memory cells, and a controller coupled to the cell array. The controller is configured to drive a voltage on the dummy word line from a first level to a second level lower than the first level. The controller is also configured to drive a voltage on the select line from the first level to the second level, such that the voltage on the select line reaches the second level after the voltage on the dummy word line reaches the second level.

Abstract: A memory includes a first deck including a first set of word lines, a second deck above the first deck and including a second set of word lines, and a controller. The controller is configured to apply a program voltage to a first target word line of the first set of word lines in the first deck, and apply a first pass voltage to at least one of the first set of word lines that is below the first target word line when applying the program voltage to the first target word line. The controller is also configured to apply the program voltage to a second target word line of the second set of word lines in the second deck, and apply a second pass voltage to at least one of the second set of word lines that is below the second target word line when applying the program voltage to the second target word line. The second pass voltage is greater than the first pass voltage.

Abstract: A device for monitoring the status of a livestock facility is disclosed, wherein the status of the livestock facility includes health and/or welfare of livestock animals inside the livestock facility, and management status of various devices installed in the facility.

Abstract: A memory device includes a top select cell, a top dummy cell and a string of memory cells. The top select cell has a first terminal coupled to a bit line and a control terminal coupled to a top select line. The top dummy cell has a control terminal coupled to a top dummy word line. The string of memory cells has control terminals coupled to respective word lines. A method operating the memory device includes prior to a program operation, applying a pre-pulse voltage to the top dummy word line, the top select line and the bit line while applying a low voltage to the word lines, and then sequentially applying the low voltage to the top dummy word line, the top select line and the bit line while applying the low voltage to the word lines.

Abstract: A memory includes a first portion, a second portion and a controller. The first portion includes a first word line to a kth word line. The second portion is formed above the first portion and includes a (k+1)th word line to an mth word line. When an xth word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to an (x?2)th word line, a second voltage to an (x?1)th word line, and a third voltage to an (x+1)th word line. x, k and m are positive integers.

Abstract: A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells, and one or more dummy word lines respectively coupled to gate terminals of the one or more dummy memory cells. The memory device further includes a control circuit configured to program a target memory cell coupled to a selected word line of the plurality of word lines. To program the target memory cell, the control circuit is configured to apply a biased dummy word line pre-pulse signal to the one or more dummy word lines in a pre-charge period prior to a programming period.

Abstract: A method of fabricating vertical cavity surface emitting laser, comprising: providing a first substrate formed with a dielectric DBR and a first bonding layer, and a second substrate formed with a etch-stop layer, a heavily doped layer, an active region, a current-confinement layer, and an arsenide DBR firstly, then sticking a third substrate on the arsenide DBR, then removing the second substrate and the etch-stop layer, next bonding the heavily doped layer to the dielectric DBR, next removing the third substrate, finally forming a p-type electrode contact and an n-type electrode contact.