Patents by Inventor Ying Hao

Ying Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250117784
    Abstract: A computer-implemented system for streamlining encryption payload of a card transaction from a transaction code transaction via a merchant inside a restricted computer network firewall. A wallet application stores data of a payment device, and the wallet application retrieves information of a merchant and a transaction via a transaction code. In response to the retrieved information, the wallet application generates an encrypted payload. The wallet application transmits the encrypted payload to a payment facilitator within the restricted computer network firewall. After decryption of the encrypted payload, the payment facilitator transmits a decrypted payload in one payment packet to the payment processing server outside the restricted computer network firewall.
    Type: Application
    Filed: November 4, 2024
    Publication date: April 10, 2025
    Applicant: Visa International Service Association
    Inventors: Pranav Sheth, Ying Hao, Vinay Gaonkar
  • Publication number: 20250067307
    Abstract: A disconnection mechanism, for engaging or disengaging a fixed component and a movable component arranged on a first shaft extending in a first direction. The disconnection mechanism includes a shift fork, connected to the movable component, and constructed to be able to reciprocate linearly in the first direction, so that the movable component is engaged with or disengaged from the fixed component. An actuator includes an output end which rotates about a rotation axis of the actuator at a distance from the rotation axis. A drive rod has a first end rotatably connected to the output end and a second end rotatably connected to the shift fork, so that the output end, when rotating, is able to drive the shift fork to reciprocate linearly.
    Type: Application
    Filed: August 20, 2024
    Publication date: February 27, 2025
    Applicant: VALEO EMBRAYAGES
    Inventors: Yifan GU, Yejin JIN, Xiaoling WANG, Ying HAO, Dongdong WANG, Xucan CHEN
  • Patent number: 12224297
    Abstract: A method of making a semiconductor structure includes forming a pixel array region on a substrate. The method further includes forming a first seal ring region on the substrate, wherein the first seal ring region surrounds the pixel array region, and the first seal ring region includes a first seal ring. The method further includes forming a first isolation feature in the first seal ring region, wherein forming the first isolation feature includes filling a first opening with a dielectric material, wherein the first isolation feature is a continuous structure surrounding the pixel array region. The method further includes forming a second isolation feature between the first isolation feature and the pixel array region, wherein forming the second isolation feature includes filling a second opening with the dielectric material.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: February 11, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Wei Cheng, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Patent number: 12203792
    Abstract: An apparatus, system and method for providing a consumable level monitor for association with a solid content-filled consumable. The embodiments may include a sensing module embedded in a label associated with the consumable suitable to sense the consumable level; and a visual indicator suitable to receive the consumable level from the sensing module, and for communicating the consumable level to a user.
    Type: Grant
    Filed: December 14, 2023
    Date of Patent: January 21, 2025
    Inventors: Amanda Williams, Julio Daniel Oropeza, Yu-Chang Lee, Ying Hao Lee, Martin Johnson, Marc Theeuwes, Stefan Vaes, Toon Diels
  • Publication number: 20250010434
    Abstract: The present disclosure relates to a steel comprising 0.8 wt % to 0.87 wt % C; 1.5 wt % to 2.3 wt % Si; 0.5 wt % to 1.3 wt % Ni; a grain refining agent, selected from the group consisting of 0.08 wt % to 0.25 wt % V, 0.015 wt % to 0.04 wt % Nb, and a combination thereof; and the balance being Fe and inevitable impurities. The present disclosure further relates to a screwdriver bit made of the steel, and a method for processing the steel.
    Type: Application
    Filed: May 28, 2024
    Publication date: January 9, 2025
    Inventors: HERNG-SHUOH JANG, YU-TING TSAI, CHUN-MING SU, YING-HAO WANG, MENG-LIN LIN
  • Publication number: 20240394345
    Abstract: Implementations of the present specification provide a digital item transfer interaction processing method and apparatus.
    Type: Application
    Filed: August 7, 2024
    Publication date: November 28, 2024
    Inventors: Jincheng DU, Weikang ZHONG, Mingxing LI, Shasha MA, Qing HE, Ying HAO
  • Publication number: 20240395571
    Abstract: An apparatus for cleaning a package device is provided. The apparatus includes a package device loader; a package device unloader; a first cleaning area disposed between the package device loader and the package device unloader; and a conveyor. The conveyor includes a frame extending from the package device loader to the package device unloader and through the first cleaning area; and a belt wrapping the frame, wherein the belt includes a movable upper surface between the package device loader and the package device unloader, wherein the movable upper surface is configured to move relative to and over the frame, and a first distance between the movable upper surface and the frame in the first cleaning area increases in a direction from the package device loader to the package device unloader.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Ying-Hao Wang, Chien-Lung Chen, Chien-Chi Tzeng, Meng-Fu Shih, Hu-Wei Lin
  • Patent number: 12154933
    Abstract: An image sensor with stress adjusting layers and a method of fabrication the image sensor are disclosed. The image sensor includes a substrate with a front side surface and a back side surface opposite to the front side surface, an anti-reflective coating (ARC) layer disposed on the back side surface of the substrate, a dielectric layer disposed on the ARC layer, a metal layer disposed on the dielectric layer, and a stress adjusting layer disposed on the metal layer. The stress adjusting layer includes a silicon-rich oxide layer. The concentration profiles of silicon and oxygen atoms in the stress adjusting layer are non-overlapping and different from each other. The image sensor further includes oxide grid structure disposed on the stress adjusting layer.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Chien Hsieh, Kuo-Cheng Lee, Ying-Hao Chen, Yun-Wei Cheng
  • Publication number: 20240387595
    Abstract: An image sensor with stress adjusting layers and a method of fabrication the image sensor are disclosed. The image sensor includes a substrate with a front side surface and a back side surface opposite to the front side surface, an anti-reflective coating (ARC) layer disposed on the back side surface of the substrate, a dielectric layer disposed on the ARC layer, a metal layer disposed on the dielectric layer, and a stress adjusting layer disposed on the metal layer. The stress adjusting layer includes a silicon-rich oxide layer. The concentration profiles of silicon and oxygen atoms in the stress adjusting layer are non-overlapping and different from each other. The image sensor further includes oxide grid structure disposed on the stress adjusting layer.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Feng-Chien HSIEH, Kuo-Cheng Lee, Ying-Hao Chen, Yun-Wei Cheng
  • Patent number: 12136086
    Abstract: A computer-implemented system for streamlining encryption payload of a card transaction from a transaction code transaction via a merchant inside a restricted computer network firewall. A wallet application stores data of a payment device, and the wallet application retrieves information of a merchant and a transaction via a transaction code. In response to the retrieved information, the wallet application generates an encrypted payload. The wallet application transmits the encrypted payload to a payment facilitator within the restricted computer network firewall. After decryption of the encrypted payload, the payment facilitator transmits a decrypted payload in one payment packet to the payment processing server outside the restricted computer network firewall.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: November 5, 2024
    Assignee: Visa International Service Association
    Inventors: Pranav Sheth, Ying Hao, Vinay Gaonkar
  • Publication number: 20240354281
    Abstract: Approaches for providing a non-disruptive file move are disclosed. A request to move a target file from the first constituent to the second constituent is received. The file has an associated file handle. The target file in the first constituent is converted to a multipart file in the first constituent with a file location for the new file in the first constituent. A new file is created in the second constituent. Contents of the target file are moved to a new file on the second constituent while maintaining access via the associated file handle via access to the multipart file. The target file is deleted from the first constituent.
    Type: Application
    Filed: April 24, 2023
    Publication date: October 24, 2024
    Applicant: NetApp, Inc.
    Inventors: Richard Parvin Jernigan, IV, Umeshkumar Vasantha Rajasekaran, Ying-Hao Wang, Yuyu Zhou
  • Patent number: 12113086
    Abstract: Apparatus and methods for sensing long wavelength light are described herein. A semiconductor device includes: a carrier; a device layer on the carrier; a semiconductor layer on the device layer, and an insulation layer on the semiconductor layer. The semiconductor layer includes isolation regions and pixel regions. The isolation regions are or include a first semiconductor material. The pixel regions are or include a second semiconductor material that is different from the first semiconductor material.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Publication number: 20240332115
    Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.
    Type: Application
    Filed: June 11, 2024
    Publication date: October 3, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Wei CHENG, Chun-Hao CHOU, Kuo-Cheng LEE, Ying-Hao CHEN
  • Publication number: 20240310614
    Abstract: An array objective lens module, having an optical axis and including a substrate, multiple lens frames, and multiple objective lens sets is provided. The substrate includes multiple accommodating vias. Each accommodating via includes an internal thread structure. The lens frames are respectively disposed in the accommodating vias. Each lens frame includes an external thread structure. The external thread structure is adapted to the internal thread structure. The objective lens sets are respectively disposed in the lens frames. Each objective lens set includes at least one lens, and a relative position of each frame and the substrate in an extension direction of the optical axis changes according to a relative rotation angle of the corresponding external read structure and internal thread structure.
    Type: Application
    Filed: December 19, 2023
    Publication date: September 19, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Chang Huang, Ying-Hao Wang, Hsing-Wei Huang, Chia-Jung Chang
  • Publication number: 20240310241
    Abstract: An array lens module calibration equipment includes a carrying platform, a visual positioning module, a laser alignment module, a depth-of-field measurement module, and a coplanarity adjustment module. An array lens module has an optical axis and includes a substrate, a calibration via through the substrate, a plurality of lens frames, and a plurality of lens sets. The visual positioning module is configured to provide a visual positioning beam and capture an image of an appearance to obtain appearance information. The laser alignment module is configured to provide a calibration laser beam so as to obtain alignment information. The depth-of-field measurement module is configured to capture a depth-of-field image to obtain depth-of-field information. The coplanarity adjustment module is configured to adjust relative positions of the plurality of lens frames relative to the substrate in an optical axis direction based on the appearance information, the alignment information, and the depth-of-field information.
    Type: Application
    Filed: December 20, 2023
    Publication date: September 19, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Chia-Jung Chang, Chang Huang, Hsing-Wei Huang, Ying-Hao Wang
  • Patent number: 12046528
    Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: July 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Patent number: 12005481
    Abstract: An embodiment system, configured to clean a semiconductor package assembly, may include a sprayer device including a plurality of nozzles configured to direct a pressurized cleaning fluid toward the semiconductor package assembly; a conveyor configured to move the semiconductor package assembly relative to the sprayer device along a first direction; and a dryer spatially displaced from the sprayer device and configured to direct a pressurized gas flow toward the semiconductor package assembly to remove cleaning fluid introduced by the sprayer device. Each of the plurality of nozzles may be displaced from one another along a second direction to thereby generate respective separate spray distribution patterns. Adjacent nozzles may be further displaced from one another along a third direction to thereby a reduce an overlap of adjacent spray distribution patterns relative to a configuration in which the adjacent nozzles are not displaced from one another along the third direction.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ying-Hao Wang, Chien-Lung Chen, Chia-Han Chuang, Jhe-Hong Wang, Chien-Chi Tzeng
  • Patent number: 12009313
    Abstract: A selective EMI shielding structure for a semiconductor package and a method of fabrication thereof is disclosed. The semiconductor package, comprising: a substrate having a first face; at least one first electronic component mounted adjacent to a first region of the first face; a least one second electronic component mounted adjacent to a second region of the first face; and an encapsulant disposed over the first and the second electronic components, wherein the encapsulant covers directly over the first electronic component, and wherein the encapsulant covers the second electronic component through a layer of conductive material.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: June 11, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Meng-Jen Wang, Chien-Yuan Tseng, Hung Chen Kuo, Ying-Hao Wei, Chia-Feng Hsu, Yuan-Long Chiao
  • Publication number: 20240183700
    Abstract: An apparatus, system and method for providing a consumable level monitor for association with a solid content-filled consumable. The embodiments may include a sensing module embedded in a label associated with the consumable suitable to sense the consumable level; and a visual indicator suitable to receive the consumable level from the sensing module, and for communicating the consumable level to a user.
    Type: Application
    Filed: December 14, 2023
    Publication date: June 6, 2024
    Inventors: Amanda Williams, Julio Daniel Oropeza, Yu-Chang Lee, Ying Hao Lee, Martin Johnson, Marc Theeuwes, Stefan Vaes, Toon Diels
  • Patent number: 11990365
    Abstract: A method for manufacturing a semiconductor device includes forming a metal layer in a substrate and sequentially forming a barrier layer and an insulating layer on the substrate. The method includes performing a first etching step to form an opening in the insulating layer, and the opening does not expose the barrier layer. After the first etching step, a gap-filling layer is formed on the insulating layer and fills the opening. The method includes performing a second etching step to form a first via communicating with the opening in the gap-filling layer, and an upper portion of the opening is widened to form a trench. The method includes performing a third etching step to remove the gap-filling layer in a bottom of the opening and to deepen both the trench and the opening. The method includes forming a second via communicating with the opening to expose the metal layer.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: May 21, 2024
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Chang-Ju Ho, Kao-Tsair Tsai, Ying-Hao Chen