Patents by Inventor Ying Hao
Ying Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240125423Abstract: A projection device includes a housing and a bracket assembly. The housing has a first side wall and a second side wall connected to each other, the first side wall has a connecting portion and a limit groove, the limit groove has a curved section and a linear section connected to each other. The second side wall has a projection hole. The bracket assembly includes an adapter and a bracket. The adapter is movably connected to the connecting portion. The bracket is pivotally connected to the adapter and has a limit post extending into the limit groove. When the limit post moves to the linear section, the adapter is adapted to move in the connecting portion and drives the limit post to move in the linear section, so the bracket can be closer to the projection hole and the effect of covering the projection hole by the bracket is improved.Type: ApplicationFiled: October 13, 2023Publication date: April 18, 2024Inventors: YING ZHANG, CHIH-HAO WU, GANG LI
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Publication number: 20240123411Abstract: A preparation method of a high-moisture-permeability fluorine-containing super-oleophobic microporous membrane is provided having the following steps: (1) preparing a white opaque mixture of fluorine-containing polymers: adding the materials in sequence according to a weight ratio of A50%˜90%:B3%˜25%:C0%˜35%:D0 %˜3%, and stirring and mixing uniformly in a non-shear manner; A is a blend of a high molecular weight polytetrafluoroethylene dispersion resin and a fluorine-containing ion exchange resin; B is a fluorine-containing alkyl acrylate monomer, or a fluorine-containing alkyl methacrylate monomer, or a mixture thereof; C is a polyurethane acrylate prepolymer, or a fluorine-free alkyl acrylate monomer, or a mixture thereof; D is a high temperature free radical initiator; (2) pouring the white opaque mixture into the blank pressing column barrel, and pressing a blank; (3) calendering into strips; (4) stretching and thermally shaping to form a membrane.Type: ApplicationFiled: December 16, 2021Publication date: April 18, 2024Applicants: Shanghai Hyproof Technology Co., Ltd., Shanghai Hyproof New Material Technology Co., LtdInventors: Huisheng WU, Ying YANG, Rongrong HAO
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Patent number: 11961892Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: GrantFiled: June 10, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 11955553Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.Type: GrantFiled: February 24, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
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Patent number: 11954895Abstract: The present disclosure discloses a method for automatically identifying south troughs by improved Laplace and relates to the technical field of meteorology. The method includes the following steps: acquiring grid data of a geopotential height field; calculating a gradient field of the geopotential height field in an x direction; searching for a turning point where a gradient value turned from being negative to being positive, and cleaning the gradient field; calculating a divergence of the x direction to obtain an improved Laplacian numerical value L?; performing 0,1 binarization processing on the L? to obtain a black-and-white image and a plurality of targets of potential troughs, merging the black-and-white image and the plurality of targets of the potential troughs by expansion, recovering original scale through erosion, and selecting an effective target through an angle of direction of a contour and an axial ratio.Type: GrantFiled: July 20, 2023Date of Patent: April 9, 2024Assignee: Chengdu University of Information TechnologyInventors: Wendong Hu, Yanqiong Hao, Hongping Shu, Tiangui Xiao, Yan Chen, Ying Zhang, Jian Shao, Jianhong Gan, Yaqiang Wang, Fei Luo, Huahong Li, Balin Xu, Qiyang Peng, Juzhang Ren, Chengchao Li, Tao Zhang, Xiaohang Wen, Chao Wang, Yongkai Zhang, Wenjie Zhou, Jingyi Tao
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Patent number: 11955501Abstract: The present disclosure describes a method for the formation of mirror micro-structures on radiation-sensing regions of image sensor devices. The method includes forming an opening within a front side surface of a substrate; forming a conformal implant layer on bottom and sidewall surfaces of the opening; growing a first epitaxial layer on the bottom and the sidewall surfaces of the opening; depositing a second epitaxial layer on the first epitaxial layer to fill the opening, where the second epitaxial layer forms a radiation-sensing region. The method further includes depositing a stack on exposed surfaces of the second epitaxial layer, where the stack includes alternating pairs of a high-refractive index material layer and a low-refractive index material layer.Type: GrantFiled: June 6, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Yu Liao, Tsai-Hao Hung, Ying-Hsun Chen
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Patent number: 11948884Abstract: A semiconductor device includes: a substrate, including an upper surface and a first to a fourth side surfaces; wherein the upper surface includes a first edge connecting the first side surface and a second edge opposite to the first edge and connecting the second side surface; a first modified trace formed on the first side surface; and a semiconductor stack formed on the upper surface, including a lower surface connecting the upper surface of the substrate, and the lower surface comprises a fifth edge adjacent to the first edge and a sixth edge opposite to the fifth edge and adjacent to the second edge; wherein a shortest distance between the first edge and the fifth edge is S1 ?m, and a shortest distance between the second edge and the sixth edge is S2 ?m; wherein in a lateral view viewing from the third side surface, the first side surface forms a first acute angle with a degree of ?1 with the vertical direction, the second side surface forms a second acute angle with a degree of ?2 with the vertical direType: GrantFiled: August 24, 2021Date of Patent: April 2, 2024Assignee: EPISTAR CORPORATIONInventors: Lin Tzu Hsiang, Chen Chih Hao, Wu Wei Che, Chen Ying Chieh
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Publication number: 20240105460Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
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Publication number: 20240101552Abstract: Provided is the carbonyl heterocyclic compound shown in formula (I) or a pharmaceutically acceptable salt thereof, capable of being used as a compound having a targeted lanthionine synthetase C-like protein 2 pathway and being used for the treatment of various conditions, including infectious diseases, autoimmune diseases, diabetes, and chronic inflammatory diseases.Type: ApplicationFiled: September 18, 2021Publication date: March 28, 2024Inventors: Chaoxin ZHANG, Guangxin XIA, Zhijun XIANG, Ying KE, Jiangsong LOU, Menghao ZHAO, Lijun HAO
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Patent number: 11942548Abstract: A multi-gate semiconductor device is formed that provides a first fin element extending from a substrate. A gate structure extends over a channel region of the first fin element. The channel region of the first fin element includes a plurality of channel semiconductor layers each surrounded by a portion of the gate structure. A source/drain region of the first fin element is adjacent the gate structure. The source/drain region includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the dielectric layer.Type: GrantFiled: May 18, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Carlos H. Diaz, Chih-Hao Wang, Wai-Yi Lien, Ying-Keung Leung
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Publication number: 20240096732Abstract: Some implementations described herein provide techniques and apparatuses for a fixture including a semiconductor die package and methods of formation. The semiconductor die package is mounted to an interposer. In addition to the semiconductor die package, the fixture includes a lid component having a top structure and footing structures that connect the lid component to the interposer. The fixture includes a thermal interface material between a top surface of the semiconductor die package and the top structure of the lid component. The footing structures, connected to the interposer using deposits of an epoxy material, provide increase a structural rigidity of the fixture relative to another fixture not including the footing structures.Type: ApplicationFiled: January 13, 2023Publication date: March 21, 2024Inventors: Chih-Hao CHEN, Li-Hui CHENG, Ying-Ching SHIH
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Publication number: 20240088225Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
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Patent number: 11929417Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: GrantFiled: June 30, 2022Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung
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Patent number: 11925440Abstract: A single smart health device able to monitor all physiological aspects of a human body includes a body fluid detection module, a temperature detection module, an electrocardiogram detection module, and a control module. The body fluid detection module tests and detects amounts of biological substances in body fluids. The temperature detection module detects a temperature of the human body. The electrocardiogram detection module detects a heart rate of the human body. The control module is electrically connected to the body fluid detection module, the temperature detection module, and the electrocardiogram detection module, and obtains the detected amounts of biological substances, the detected temperature, and the detected heart rate.Type: GrantFiled: June 19, 2020Date of Patent: March 12, 2024Assignee: Jiangyu Kangjian Innovation Medical Technology(Chengdu) Co., LtdInventors: Yu-Chao Li, Lien-Yu Lin, Ying-Wei Sheng, Chieh Kuo, Ping-Hao Liu
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Patent number: 11923396Abstract: An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.Type: GrantFiled: April 18, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Wei Hsu, Tsai-Hao Hung, Chung-Yu Lin, Ying-Hsun Chen
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Publication number: 20240071847Abstract: A semiconductor package including two different adhesives and a method of forming are provided. The semiconductor package may include a package component having a semiconductor die bonded to a substrate, a first adhesive over the substrate, a heat transfer layer on the package component, and a lid attached to the substrate by a second adhesive. The first adhesive may encircle the package component and the heat transfer layer. The lid may include a top portion on the heat transfer layer and the first adhesive, and a bottom portion attached to the substrate and encircling the first adhesive. A material of the second adhesive may be different from a material of the first adhesive.Type: ApplicationFiled: August 26, 2022Publication date: February 29, 2024Inventors: Yi-Huan Liao, Ping-Yin Hsieh, Chih-Hao Chen, Pu Wang, Li-Hui Cheng, Ying-Ching Shih
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Publication number: 20240071535Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.Type: ApplicationFiled: October 16, 2022Publication date: February 29, 2024Applicant: United Microelectronics Corp.Inventors: Chung-Hao Chen, Chi-Hsiu Hsu, Chi-Fa Lien, Ying-Ting Lin, Cheng-Hsiao Lai, Ya-Nan Mou
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Publication number: 20240069067Abstract: A test device includes a power compensation module and a test module. The power compensation module receives AC power generated by a device under test to generate DC power to the device under test. The test module provides a plurality of test signals and a test mode to the device under test for testing the device under test.Type: ApplicationFiled: December 5, 2022Publication date: February 29, 2024Inventors: Wei-Chih HUNG, Ying-Ping CHIANG, Yu-Ren RUAN, Chia-Hao WU
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Patent number: D1016746Type: GrantFiled: September 8, 2021Date of Patent: March 5, 2024Assignee: Jiangyu Kangjian Innovation Medical Technology(Chengdu) Co., LtdInventors: Chieh Kuo, Ying-Wei Sheng, Ping-Hao Liu
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Patent number: D1018775Type: GrantFiled: April 19, 2023Date of Patent: March 19, 2024Assignee: ROHM AND HAAS ELECTRONIC MATERIALS SINGAPORE PTE, LTDInventors: Robert James McMahon, Ying Hao Teo, Tomasz Swiatek