Patents by Inventor Ying Huang

Ying Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12369399
    Abstract: An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nanoribbons) and a second semiconductor body (e.g., set of one or more nanoribbons) above the first semiconductor body. The first and second semiconductor bodies are part of the same fin structure. The distance between an upper surface of the first semiconductor body and a lower surface of the second semiconductor body is 60 nm or less. A first gate structure is on the first semiconductor body, and a second gate structure is on the second semiconductor body. An isolation structure that includes a dielectric material is between the first and second gate structures, and is on and conformal to a top surface of the first gate structure. In addition, a bottom surface of the second gate structure is on a top surface of the isolation structure, which is relatively flat.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: July 22, 2025
    Assignee: INTEL CORPORATION
    Inventors: Willy Rachmady, Sudipto Naskar, Cheng-Ying Huang, Gilbert Dewey, Marko Radosavljevic, Nicole K. Thomas, Patrick Morrow, Urusa Alaan
  • Publication number: 20250232551
    Abstract: An object detection method and an object detection apparatus are disclosed. In the object detection method, a bitstream of a progressively encoded JPEG image is fetched from an image supply device, wherein the bitstream includes a header and a subset of a plurality of discrete cosine transform (DCT) coefficients of the JPEG image, the subset of the DCT coefficients is decoded according to information in the header to reconstruct a coarse scan image of the JPEG image; and an object detection is performed on the coarse scan image to detect an object in the JPEG image.
    Type: Application
    Filed: January 11, 2024
    Publication date: July 17, 2025
    Applicant: HIMAX TECHNOLOGIES LIMITED
    Inventors: Tzu-Hsu Chen, Bo-Ying Huang, Ti-Wen Tang
  • Publication number: 20250227934
    Abstract: A method is provided. The method includes applying a first pulse to a ferroelectric memory device, measuring a memory window metric of the ferroelectric memory device, and applying a second pulse to the ferroelectric memory device. The first pulse may have a first voltage magnitude. The second pulse may have a second voltage magnitude. The second voltage magnitude may be determined based at least in part on the measured memory window metric.
    Type: Application
    Filed: January 8, 2024
    Publication date: July 10, 2025
    Inventors: YU-CHUAN SHIH, YU-KAI CHANG, PEI-CHUN LIAO, HUAI-YING HUANG, CHUN-CHIEH LU, YU-MING LIN
  • Patent number: 12356749
    Abstract: An image sensor device is provided. The image sensor device includes a substrate having a front surface, a back surface, and a light-sensing region. The image sensor device includes a first isolation structure extending from the front surface into the substrate. The first isolation structure surrounds a first portion of the light-sensing region, the first isolation structure has an etch stop layer, the etch stop layer has an end portion, and the end portion has an H-like shape. The image sensor device includes a second isolation structure extending into the substrate from the back surface to the end portion. The second isolation structure surrounds a second portion of the light-sensing region.
    Type: Grant
    Filed: October 16, 2023
    Date of Patent: July 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang
  • Publication number: 20250212417
    Abstract: A semiconductor structure includes a gate layer, a ferroelectric layer, a source structure, a drain structure, an oxide semiconductor and a high-k material layer. The gate layer is disposed in an interconnect structure. The ferroelectric layer is disposed over the gate layer. The source structure and the drain structure are disposed over the ferroelectric layer. The oxide semiconductor is disposed over the ferroelectric layer and between the source structure and the drain structure. The high-k material layer is disposed on and contacts a surface of the ferroelectric layer. A method of manufacturing the semiconductor structure is also provided.
    Type: Application
    Filed: December 25, 2023
    Publication date: June 26, 2025
    Inventors: YU-CHUAN SHIH, CHUN-CHIEH LU, KUO-CHANG CHIANG, CHIH-YU CHANG, HUAI-YING HUANG, YU-MING LIN
  • Patent number: 12342614
    Abstract: Techniques are provided herein to form semiconductor devices having a stacked transistor configuration. An n-channel device and a p-channel device may both be gate-all-around (GAA) transistors each having any number of nanoribbons extending in the same direction where one device is located vertically above the other device. According to some embodiments, the n-channel device and the p-channel device conductively share the same gate, and a width of the gate structure around one device is greater than the width of the gate structure around the other device. According to some other embodiments, the n-channel device and the p-channel device each have a separate gate structure that is isolated from the other using a dielectric layer between them. A gate contact is adjacent to the upper device and contacts the gate structure of the other lower device.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: June 24, 2025
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Patrick Morrow, Arunshankar Venkataraman, Sean T. Ma, Willy Rachmady, Nicole K. Thomas, Marko Radosavljevic, Jack T. Kavalieros
  • Patent number: 12338328
    Abstract: A reversible stress-responsive material, a preparation method, and a use thereof are provided. The reversible stress-responsive material has the property of real-time reversible force response at room temperature. When used with crosslinked plastic (high Tg) and rubber (low Tg) polymer materials, the reversible stress-responsive material can significantly enhance the mechanical strength and ductility of covalently cross-linked polymers. the triazolinedione (TAD)-indole click chemistry with the force-induced reversible property is used to construct a force-reversible crosslinked polymer material, and such a force-induced reversible crosslinking method can achieve the breakage and re-forming of covalent crosslinking points at room temperature in a solid state without any external stimuli other than the ambient temperature. This room-temperature force-induced reversible C—N covalent crosslinking can be regarded as an innovative approach to designing a high-toughness polymer material.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: June 24, 2025
    Assignees: Southwest University of Science and Technology, Sichuan Guanmusi Yang New Material Technology Co LTD
    Inventors: Guanjun Chang, Li Yang, Yewei Xu, Ying Huang, Rui Yuan, Mengqi Du
  • Publication number: 20250180024
    Abstract: A fluid driving device includes a housing, a sleeve member, a bearing unit, a shaft member, a rotor, a fastener member and a screw. The housing has an accommodation space, an inlet passage unit spatially communicating with the accommodation space and an external environment, and an outlet passage unit spatially communicating with the accommodation space and the external environment. The sleeve member includes a tubular sleeve wall, and a drainage hole set formed through the tubular sleeve wall and spatially communicating with the inlet passage unit. The drainage hole set has a plurality of drainage holes arranged about an axis, and respectively extending along a plurality of central lines. The bearing unit is disposed in the sleeve member. The shaft member includes a driven segment and a support segment. The rotor is secured to the driven segment and includes a plurality of blades.
    Type: Application
    Filed: December 3, 2024
    Publication date: June 5, 2025
    Applicant: Hold Well Industrial Co., Ltd.
    Inventors: Shih-Ying HUANG, Jui-Ming Huang
  • Publication number: 20250185363
    Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.
    Type: Application
    Filed: January 31, 2025
    Publication date: June 5, 2025
    Inventors: Seung Hoon SUNG, Cheng-Ying HUANG, Marko RADOSAVLJEVIC, Christopher M. NEUMANN, Susmita GHOSE, Varun MISHRA, Cory WEBER, Stephen M. CEA, Tahir GHANI, Jack T. KAVALIEROS
  • Patent number: 12323092
    Abstract: A tracking type flexible photovoltaic bracket is provided, including photovoltaic assemblies, pillars, a driving member, direction-changing mechanisms, and two pulling ropes. Each of the pillars is disposed with a double-rope grooved wheel. The driving member is configured to drive the double-rope grooved wheel arranged on an end of the driving member to rotate. The direction-changing mechanisms are arranged corresponding ones of the pillars in one-to-one manner. Each of the direction-changing mechanisms includes a worm gear assembly and a curved plate assembly. Each of the corresponding ones of the pillars is rotatably connected with the worm gear assembly and the curved plate assembly, and a bottom of the curved plate assembly is disposed with a gear rack. First ends and second ends of the two pulling ropes are wound on the respective double-rope grooved wheels being respectively located on the first ends and the second ends.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: June 3, 2025
    Assignee: XI'AN UNIVERSITY OF ARCHITECTURE AND TECHNOLOGY
    Inventors: Ying Huang, Yanfei Zhu, Yanan Guo
  • Publication number: 20250175860
    Abstract: A method of wireless communication is described. A method of wireless communication, comprising transmitting, from an integrated access and backhaul (IAB) node to an IAB donor, IAB node mobility status information.
    Type: Application
    Filed: January 27, 2025
    Publication date: May 29, 2025
    Inventors: Ying HUANG, Lin CHEN
  • Patent number: 12315560
    Abstract: A device is disclosed, including a latch circuit, a first pass-gate transistor, and a second pass-gate transistor. The latch circuit stores a bit data and is arranged in a first layer. The first pass-gate transistor and the second pass-gate transistor are arranged in a second layer separated from the first layer. The first pass-gate transistor is coupled between a first bit line and a first terminal of the latch circuit, and the second pass-gate transistor is coupled between a second bit line and a second terminal of the latch circuit.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: May 27, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huai-Ying Huang, Yu-Ming Lin
  • Publication number: 20250155472
    Abstract: A test fixture assembly is for performing a test of a DUT (Device under Test), the DUT includes a plurality of pins exposed on a surface of the DUT, and the test fixture assembly includes a circuit board and a socket unit. The circuit board includes a plurality of test pads, which are exposed on a surface of the circuit board. The socket unit includes a socket base and a plurality of socket probes, which are inserted through the socket base. A first end and a second end of each of the socket probes are respectively exposed on two opposite surfaces of the socket base. Each of the test pads, a corresponding one of the socket probes and a corresponding one of the pins are configured to be linearly arranged along a socket probe direction.
    Type: Application
    Filed: November 7, 2024
    Publication date: May 15, 2025
    Inventors: HAO LIANG HUNG, CHUN YING HUANG, KUANG TING CHI, YU CHENG LIU
  • Publication number: 20250155485
    Abstract: An antenna test assembly includes a DUT (Device under Test). The DUT includes an antenna module and a circuit board. The antenna module includes a first antenna element, which includes a first antenna pin and a second antenna pin. The circuit board includes a first line and a second line, and two ends of each of the first line and the second line are electrically connected to two metal pads, respectively, exposed on the circuit board. When the antenna test assembly is in an equipment test mode, the first line, the first antenna pin, the second antenna pin and the second line are electrically connected in sequence.
    Type: Application
    Filed: October 23, 2024
    Publication date: May 15, 2025
    Inventors: HAO LIANG HUNG, CHUN YING HUANG, YU CHENG LIU
  • Publication number: 20250149387
    Abstract: Various embodiments of the present disclosure are directed towards a method for non-destructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image to determine ROI pixels. The ROI pixels are remaining pixels after the subtracting and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored based on gray levels of the ROI pixels. Further, the wafer is processed based on the score.
    Type: Application
    Filed: December 27, 2024
    Publication date: May 8, 2025
    Inventors: I-Che Lee, Huai-Ying Huang, Yi Chien Lee
  • Publication number: 20250144073
    Abstract: A novel prophylactic therapy for cancer, as well as therapy against DNA damage, inflammation and immunosuppression involves the ?-blocker carvedilol, which is a racemic mixture consisting of two enantiomers, S- and R-carvedilol, in 1:1 ratio. S-carvedilol is a ?-blocker, with a highly potent antagonizing activity against the ?-adrenergic receptors, which is the main mechanism for the drug's pharmacological activity in treatment of high blood pressure and heart failure. Carvedilol—the racemic mixture—prevents ultraviolet radiation induced skin cancer by attenuating DNA damage, reducing inflammation and reversing immunosuppression. The non-?-blocking enantiomer R-carvedilol exhibits the same cancer preventive efficacy as the racemic carvedilol, without disturbing the cardiovascular system. Both carvedilol and R-carvedilol prevent chemical carcinogen-induced lung cancer development and lung inflammation.
    Type: Application
    Filed: June 10, 2024
    Publication date: May 8, 2025
    Inventors: Ying Huang, Bradley Tram Andresen, Jinghua Jeffrey Wang, Vijay Kumar Nekkanti, Aysz Shahid
  • Patent number: 12292086
    Abstract: The bearing seat device includes a bearing seat, a bearing set, a driven module, and an adjusting member. The bearing seat has a mounting hole, an adjusting slot, and an inserting hole. The adjusting slot divides a section of the bearing seat that is adjacent to the inserting hole and the mounting hole into a first side compartment and a second side compartment. The inserting hole extends from the first side compartment to the second side compartment. The bearing set is mounted in the mounting hole. The driven module extends into the mounting hole, is supported by the bearing set, and is rotatable relative to the bearing seat. The adjusting member engages the mounting hole and is operable to adjust a width of the adjusting slot between the first and the second side compartments and a diameter of the mounting hole.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: May 6, 2025
    Assignee: Hold Well Industrial Co., Ltd.
    Inventors: Kuan-Ta Chen, Shih-Ying Huang
  • Publication number: 20250140329
    Abstract: Upon determining that a first read operation on one memory cell of memory cells has failed, a second read operation on the memory cell is started. In the second read operation, a second pass voltage is applied to second word line, and a first pass voltage is applied to third word line. The second word line include one or more word lines adjacent to a selected word line, and the third word line include remaining unselected word lines. The selected word line corresponds to the memory cell to be read. The first pass voltage includes a voltage applied to the second word line in the first read operation. The second pass voltage is higher than the first pass voltage.
    Type: Application
    Filed: January 6, 2025
    Publication date: May 1, 2025
    Inventors: Hongtao Liu, Lei Jin, Xiangnan Zhao, Ying Huang, Lei Guan, Yuanyuan Min
  • Patent number: 12289692
    Abstract: A method for improving transmission power management with compliance to regulations of radiofrequency exposure, which may comprise: at a current time, estimating whether a window average power, which may reflect average power transmitted using a radio technology during a moving time window, will exceed a power limit after the current time; if true, proceeding to at least one of a first handling subroutine and a second handling subroutine to set a power cap, and causing power transmitted to be capped by the power cap after the current time. The first handling subroutine may comprise: scheduling to set the power cap lower at a scheduled time. Estimating whether the window average power will exceed the power limit may involve discarding one of a plurality of power records. The second handling subroutine may comprise: setting the power cap not higher than the discarded one of the plurality of power records.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: April 29, 2025
    Assignee: MEDIATEK INC.
    Inventors: Yi-Hsuan Lin, Han-Chun Chang, Chih-Yuan Lin, Yi-Ying Huang
  • Patent number: D1080822
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: June 24, 2025
    Assignee: Grand Mate Co., Ltd.
    Inventors: Chin-Ying Huang, Hsin-Ming Huang, Hsing-Hsiung Huang, Yen-Jen Yeh