Patents by Inventor Ying Huang

Ying Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250087485
    Abstract: Aspects of the present disclosure relate to apparatus, systems, and methods of using atomic hydrogen radicals with epitaxial deposition. In one aspect, nodular defects (e.g., nodules) are removed from epitaxial layers of substrate. In one implementation, a method of processing substrates includes selectively growing an epitaxial layer on one or more crystalline surfaces of a substrate. The epitaxial layer includes silicon. The method also includes etching the substrate to remove a plurality of nodules from one or more non-crystalline surfaces of the substrate. The etching includes exposing the substrate to atomic hydrogen radicals. The method also includes thermally annealing the epitaxial layer to an anneal temperature that is 600 degrees Celsius or higher.
    Type: Application
    Filed: November 21, 2024
    Publication date: March 13, 2025
    Inventors: Chen-Ying WU, Yi-Chiau HUANG, Zhiyuan YE, Schubert S. CHU, Errol Antonio C. SANCHEZ, Brian Hayes BURROWS
  • Publication number: 20250084870
    Abstract: A cover used in a ventilation fan includes a noise reduction structure and a shelter. The noise reduction structure has an air inlet, a flat portion surrounding the air inlet, and a peripheral portion surrounding the flat portion. The sidewall of the flat portion extends in a vertical direction from the peripheral portion. The bottom surface of the flat portion extends in a horizontal direction from the sidewall, and is a flat surface. The shelter is disposed on the peripheral portion and covers the air inlet.
    Type: Application
    Filed: August 8, 2024
    Publication date: March 13, 2025
    Inventors: Ying-Huang CHUANG, Wen-Chih LI, Chun-Wei CHEN
  • Publication number: 20250085476
    Abstract: A photonic device includes a silicon layer, wherein the silicon layer includes a waveguide portion. The photonic device further includes a cladding layer over the waveguide portion, wherein the cladding layer partially exposes a surface of the waveguide portion. The photonic device further includes a low refractive index layer in direct contact with the cladding layer, wherein the low refractive index layer comprises silicon oxide, silicon carbide, silicon oxynitride, silicon carbon oxynitride, aluminum oxide or hafnium oxide. The photonic device further includes an interconnect structure over the low refractive index layer.
    Type: Application
    Filed: November 21, 2024
    Publication date: March 13, 2025
    Inventors: Chien-Ying WU, Yuehying LEE, Sui-Ying HSU, Chen-Hao HUANG, Chien-Chang LEE, Chia-Ping LAI
  • Publication number: 20250082727
    Abstract: The present invention provides a method and a pharmaceutical composition for cartilage regeneration or treatment of a cartilage defect disease, e.g., degenerative osteoarthritis, which comprises CXCL14 protein, or the peptide fragment thereof. The method and pharmaceutical composition could further comprise stem cell-derived extracellular vesicles.
    Type: Application
    Filed: September 6, 2024
    Publication date: March 13, 2025
    Applicant: FAR EASTERN MEMORIAL HOSPITAL
    Inventors: Hsiu-Jung LIAO, Chih-Hung CHANG, Yi-Shan SHEN, Chi-Ying HUANG
  • Publication number: 20250081910
    Abstract: Present invention teaches the method of using a keratin hydrolysis peptide (“KHP”) solution to enhance the drought-tolerance of the cotton plant. By selectively choosing specific weights of feathers and water, and treating the mixture, though one embodiment does not have water mixed in, to a high-temperature high-pressure hydrolysis process, the resulting solution is confirmed to contain at least 253 peptides and then applied to the cotton seeds and the soil around the cotton plants. Optionally, the KHP solution can be diluted by water, as taught in the specification, before applying to the seeds and the soil as taught herein.
    Type: Application
    Filed: December 12, 2023
    Publication date: March 13, 2025
    Applicant: CH Biotech R&D Co., Ltd.
    Inventors: Jenn Wen HUANG, Yi-Chiao CHAN, Meng-Ying LI
  • Patent number: 12247081
    Abstract: Provided are bispecific or multispecific antibodies that include an anti-CEACAM5 portion and one or more anti-4-1BB nanobodies whose agonist activity is dependent on the presence of the CEACAM5 antigen. Such bispecific or multispecific antibodies are safe, and are efficacious in treating cancer and have long-term protective immunological memory against tumors. Methods of using the antibodies for treating diseases such as cancer are also provided.
    Type: Grant
    Filed: May 8, 2024
    Date of Patent: March 11, 2025
    Assignee: LANOVA MEDICINES LIMITED
    Inventors: Runsheng Li, Wei Cao, Ying Qin Zang, Wentao Huang
  • Publication number: 20250076370
    Abstract: An IC test method, comprising: electrically connecting a circuit board to a first IC; generating a first test signal to test the first IC; electrically connecting the circuit board to a first adaption board, and electrically connecting a second IC to the first adaption board, wherein a first connection mechanism between the first IC and the circuit board and a second connection mechanism between the second IC and the circuit board are different; and generating a second test signal to test the second IC by the control IC.
    Type: Application
    Filed: August 27, 2024
    Publication date: March 6, 2025
    Applicant: Realtek Semiconductor Corp.
    Inventors: Jian-Xing Huang, Ting-Ying Wu, Chin-Yuan Lo, Hsin-Hui Lo
  • Publication number: 20250076369
    Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.
    Type: Application
    Filed: April 16, 2024
    Publication date: March 6, 2025
    Applicant: MEDIATEK INC.
    Inventors: Ronald Kuo-Hua Ho, Kun-Yu Wang, Yen-Chang Shih, Sung-Te Chen, Cheng-Han Wu, Yi-Ying Liao, Chun-Ming Huang, Yen-Feng Lu, Ching-Yu Tsai, Tai-Lai Tung, Kuan-Fu Lin, Bo-Kang Lai, Yao-Syuan Lee, Tsyr-Rou Lin, Ming-Chao Tsai, Li-Hsuan Chiu
  • Publication number: 20250075441
    Abstract: A top-down construction type assembly construction method for paved road surface, including the following steps: step I, manufacturing prefabricating slabs: using a top-down method to manufacture the prefabricating slabs, and providing bolt sleeves, inside the prefabricating slabs, which are evenly arranged in the prefabricating slabs; step II, mounting the prefabricating slabs: on a lower bearing plate, placing the prefabricating slabs in one step, performing a fine tuning on a position and an altitude of the prefabricating slabs, performing a grouting construction, finally forming the paved road surface; the prefabricating slabs are manufactured by laying bricks and pouring concrete, the prefabricating slabs are rolled over and mounted, thus eliminating on-site concrete bonding between bricks and the lower bearing plate, improving overall stability of the bricks and the prefabricating slabs after being mounted, assembled mounting for a paved road surface is implemented, and the construction period is shorte
    Type: Application
    Filed: October 28, 2024
    Publication date: March 6, 2025
    Inventors: Jiesheng ZHANG, Yangjie JIANG, Fengchun DONG, Wu HUANG, Anhui WANG, Shengyun HE, Jingyi LI, Shijun PI, Lingjian KONG, Ning ZHAO, Zhuoyi WEI, Shuguo XU, Ying WANG, Can JIANG, Bo ZHANG
  • Publication number: 20250076607
    Abstract: A camera structure, including a lens holder, a lens frame and a plurality of balls. The lens holder has a holder body, one end of which has a first rolling groove. The first groove wall part and the second groove wall part are disposed on two sides of the first rolling groove, and the groove bottom is disposed between the first groove wall part and the second groove wall part. The lens frame is mounted on an outer side of the holder body. The plurality of balls are located inside the first rolling groove, wherein the first groove wall part and the second groove wall part support the plurality of balls, there is a gap between each of the plurality of balls and the groove bottom, and the plurality of balls lay between the lens holder and the lens frame.
    Type: Application
    Filed: May 29, 2024
    Publication date: March 6, 2025
    Applicant: Lanto Electronic Limited
    Inventors: Ngoc-Luong NGUYEN, Wei-Han HSIA, Po-Ying TSENG, Wen-Yen HUANG, Shang-Yu HSU, Fu-Yuan WU
  • Patent number: 12243875
    Abstract: Embodiments disclosed herein include forksheet transistor devices having a dielectric or a conductive spine. For example, an integrated circuit structure includes a dielectric spine. A first transistor device includes a first vertical stack of semiconductor channels spaced apart from a first edge of the dielectric spine. A second transistor device includes a second vertical stack of semiconductor channels spaced apart from a second edge of the dielectric spine. An N-type gate structure is on the first vertical stack of semiconductor channels, a portion of the N-type gate structure laterally between and in contact with the first edge of the dielectric spine and the first vertical stack of semiconductor channels. A P-type gate structure is on the second vertical stack of semiconductor channels, a portion of the P-type gate structure laterally between and in contact with the second edge of the dielectric spine and the second vertical stack of semiconductor channels.
    Type: Grant
    Filed: January 10, 2024
    Date of Patent: March 4, 2025
    Assignee: Intel Corporation
    Inventors: Seung Hoon Sung, Cheng-Ying Huang, Marko Radosavljevic, Christopher M. Neumann, Susmita Ghose, Varun Mishra, Cory Weber, Stephen M. Cea, Tahir Ghani, Jack T. Kavalieros
  • Publication number: 20250068542
    Abstract: A computer-implemented method includes identifying a webpage comprising a set of user interface (UI) elements, analyzing the set of user UI elements to identify a set of interactable elements, classifying the elements of the set interactable elements as either focusable or not focusable, extracting features from source code corresponding to interactable elements of the set of interactable elements classified as focusable, and building an accessibility issue detection model using the extracted features from source code corresponding to focusable interactable elements as training data. The method may further include extracting features from source code corresponding to interactable elements classified as not focusable and updating the accessibility issue detection model using the extracted features from source code corresponding to interactable elements which are not focusable as training data.
    Type: Application
    Filed: August 21, 2023
    Publication date: February 27, 2025
    Inventors: Yuan Jie Zhang, Yi Chen Huang, Bo Zhang, Tony Ping-Chung YANG, Huai Ying HY Xia
  • Publication number: 20250069659
    Abstract: A memory circuit includes a plurality of bitcells coupled to a plurality of bitlines, a plurality of wordlines, a plurality of source lines, and a control line. A first of the bitcells and a second of the bitcells are coupled to a first of the bitlines. The first bitcell is coupled to a first of the source lines. The second bitcell is coupled to a second of the source lines. The first source line is different from the second source line.
    Type: Application
    Filed: November 15, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yih WANG, Tung-Cheng CHANG, Perng-Fei YUH, Gu-Huan LI, Chia-En HUANG, Chun-Ying LEE
  • Publication number: 20250066814
    Abstract: A baculovirus vector and a use thereof in the preparation of a recombinant adeno-associated virus (rAAV) in an insect cell are provided. The baculovirus vector includes an exogenous gene expression cassette and a stable sequence. The stable sequence is located at a site 5 kb or less from the exogenous gene expression cassette, and the stable sequence is a conserved noncoding element (CNE) sequence or a nucleocapsid assembly-essential element (NAE) sequence. When an insect cell is infected with a recombinant baculovirus (rBV) constructed in this way, after multiple continuous passages, production levels of the rBV and the rAAV still remain relatively stable.
    Type: Application
    Filed: November 15, 2024
    Publication date: February 27, 2025
    Applicant: GENEVOYAGER (WUHAN) CO., LTD.
    Inventors: He XIAO, Xiaobin HE, Gang HUANG, Ying HU, Xing PAN, Mengdie WANG, Liang DU
  • Patent number: 12236837
    Abstract: A power supply circuit, a driving method thereof, a printed circuit board, a display module and a display apparatus are disclosed, which relates to a technical field of displaying. The power supply circuit includes a first power management chip and a second power management chip configured to be respectively connected with a display panel and provide different driving signals to the display panel, and the driving signals are configured for driving the display panel to display.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: February 25, 2025
    Assignees: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE Technology Group Co., Ltd.
    Inventors: Ying Zhang, Jin Sha, Can Shen, Xiang Fang, Bo Ran, Chao Gao, Yao Chen, Yiming Cheng, Jinxiang Li, Shifei Huang, Shengjie Yin, Pan Chen, Jun Tao, Wendi Zhang, Zhou Zhang, Qiuju Xie, Jun Wei, Hongchao Su
  • Publication number: 20250063744
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a substrate comprising first opposing sidewalls defining a first trench and second opposing sidewalls defining a second trench laterally offset from the first trench. A stack of layers comprises a plurality of conductive layers and a plurality of dielectric layers alternatingly stacked with the conductive layers. The stack of layers comprises a first segment in the first trench and a second segment in the second trench. A first lateral distance between the first segment and the second segment aligned with a first surface of the substrate is greater than a second lateral distance between the first segment and the second segment below the first surface of the substrate.
    Type: Application
    Filed: November 7, 2024
    Publication date: February 20, 2025
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Alexander Kalnitsky, Shih-Fen Huang, Shu-Hui Su, Ting-Chen Hsu, Tuo-Hsin Chien, Felix Ying-Kit Tsui, Shi-Min Wu, Yu-Chi Chang
  • Publication number: 20250063720
    Abstract: A semiconductor device includes a substrate, an interconnect, a memory cell, and a plurality of first barrier structures. The interconnect is disposed over the substrate. The memory cell is disposed in the interconnect within a memory region of the substrate, where the memory cell includes a transistor and a capacitor. The transistor includes a gate, source/drain elements respectively standing at two opposite sides of the gate, and a channel disposed between the source/drain elements and overlapped with the gate. The capacitor is disposed over the transistor and electrically coupled to one of the source/drain elements. The plurality of first barrier structures line sidewalls and bottom surfaces of the source/drain elements, and each include a first barrier layer and a second barrier layer disposed between the source/drain elements and the first barrier layer, where a first absorption interface is disposed between the first barrier layer and the second barrier layer.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 20, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Che Lee, Huai-Ying Huang, Yen-Chieh Huang, Wei-Gang Chiu, Kai-Wen Cheng, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20250058324
    Abstract: An automated molecular operating system includes at least one centrifuge tube carrying module, a transport module, a plurality of temperature control modules, a capping module, a magnetic field module and an automated processing module. The automated processing module is electrically connected to the transport module, the temperature control modules, the capping module and the magnetic field module, and controls the transport module to move the centrifuge tube carrying module, so that a centrifuge tube contained in the centrifuge tube carrying module makes a reaction in the temperature control modules, and the magnetic field module or the capping module is provided to the centrifuge tube according to requirements, such that a specimen in the centrifuge tube can be automatically subjected to nucleic acid extraction, nucleic acid amplification, primer labeling, reverse transcription or a combination thereof, thereby reducing manual operation errors and increasing the ease of operation.
    Type: Application
    Filed: November 17, 2023
    Publication date: February 20, 2025
    Inventors: Yi-Fang CHEN, Suz-Kai HSIUNG, Chun-Wei HUANG, Yin-Lin LI, Yu-Ying WU
  • Patent number: D1062803
    Type: Grant
    Filed: March 14, 2024
    Date of Patent: February 18, 2025
    Inventors: Li Chu, Ying Huang, Zhe Zhu
  • Patent number: D1063525
    Type: Grant
    Filed: June 9, 2023
    Date of Patent: February 25, 2025
    Assignee: GRAND MATE CO., LTD.
    Inventors: Chin-Ying Huang, Hsin-Ming Huang, Hsing-Hsiung Huang, Yen-Jen Yeh