Abstract: A roasting drum and a manufacturing method thereof including a drum body and at least one agitator blade. The drum body includes a drum wall which provides with at least one fixing hole, the at least one fixing hole passing through an inner surface and an outer surface of the drum wall. The at least one agitator blade is disposed in the drum body and is provided with at least one fixing convex part which passes through the at least one fixing hole. The agitator blade can be positioned in the drum body and is not easily displaced when assembling.

Abstract: A coffee bean roaster includes a machine body, a roasting drum, a heating device and a fan module. The machine body includes a casing, a partition assembly, a receiving trough and a container. The partition assembly is disposed inside the casing and partitions the inside of the casing into a first chamber, a second chamber and a third chamber. The receiving trough is disposed outside casing and communicates with the first chamber, and the container is disposed in the receiving trough and has a plurality of mesh holes communicating with the receiving trough. The roasting drum is rotatably disposed inside the second chamber of the casing, wherein one side of the roasting drum has a plurality of through holes communicating with the third chamber. The heating device is disposed inside the second chamber for heating the roasting drum. The fan module is attached to the casing for pumping air to the outside of the casing through the first chamber and the third chamber.

Abstract: A roasting drum of a coffee bean roaster including a drum body, an end plate and a plurality of guide vanes. The end plate is coupled to an end of the drum body and has a plurality of through holes communicating with an inside and an outside of the drum body, each of the through holes is elongated and extends along a radial direction of the end plate. The guide vanes are connected to the end plate and disposed respectively at one side of the through holes. With the flow guiding of the guide vanes, the airflow inside the roasting drum of the coffee bean roaster is efficiently accelerated.

Abstract: A high-performance distributed fiber sensing system based on EHz ultrafast pulse scanning. During testing of a disturbance signal, an internally frequency converted pulse light emitted by an EHz ultrafast pulse scanning laser enters a sensing fiber after passing through a circulator, and a backward Rayleigh scattering signal transmitted by the sensing fiber enters an unbalanced Michelson interferometer after passing through a coupler. By designing an arm length difference between two interference arms, interferences sequentially occur for the backward Rayleigh scattering light at a position where lengths of two adjacent arms differ. A signal received after passing through the unbalanced Michelson interferometer includes a phase difference signal caused by an external disturbance signal in the sensing fiber.

Abstract: An EHz ultrafast modulated pulse scanning laser and a distributed fiber sensing system. A plurality of phase-shift gratings are engraved on a doped fiber, the phase-shift gratings having different central window wavelengths and a wavelength interval between the adjacent central window wavelengths being a preset fixed value. When a pump light emitted by a pump laser source is coupled by a wavelength division multiplexer and enters the doped fiber, a single-mode narrow-linewidth laser light having multiple wavelengths with a wavelength interval being a preset fixed value can be generated, by using the phase-shift gratings graved on the doped fiber. The ultrafast modulation is completed by using a time-domain control method based on an EOM. An internally frequency converted pulse light formed by splicing pulse lights whose frequencies linearly increase is obtained, thus forming the EHz ultrafast modulation of a distributed feedback fiber laser.

Abstract: A self-check system and a method thereof are disclosed. In the self-check system, a memory stores a safety check program, a main application program and a predetermined checksum data. The safety check program include a circuit check program, a watchdog circuit reset program and a checksum check program. When a chip system is powered on, a processing unit executes the main application program, and then executes an interrupt call to generate an interrupt, so as to execute the safety check program and the circuit check program to check a to-be-checked circuit. The processing unit also executes the watchdog circuit reset program to reset a counting value of a watchdog circuit. The processing unit also executes the checksum check program to calculate a checksum data of the first safety check program, and reset the chip system when the calculated checksum data is not equal to the predetermined checksum data.

Abstract: Disclosed herein are tri-gate and all-around-gate transistor arrangements, and related methods and devices. For example, in some embodiments, a transistor arrangement may include a channel material disposed over a substrate; a gate electrode of a first tri-gate or all-around-gate transistor, disposed over a first part of the channel material; and a gate electrode of a second tri-gate or all-around-gate transistor, disposed over a second part of the channel material. The transistor arrangement may further include a device isolation structure made of a fixed charge dielectric material disposed over a third part of the channel material, the third part being between the first part and the second part of the channel material.

Abstract: The present invention relates to use of antipsychotic phenothiazine derivative for treatment of cancer. The invention also provides a use for manufacture a medicament, a pharmaceutical composition and a method for treating a cancer, and/or preventing or delaying cancer recurrence based on trifluoperazine. The invention further provides a use for manufacture a medicament, a pharmaceutical composition and a method for treating cancer based on thioridazine and its enantiomers. Additionally, the invention provides a use for manufacture a medicament, a pharmaceutical composition and a method for treating KRAS mutant NSCLC comprising thioridazine.

Abstract: The present invention provides solid forms of an MK2 inhibitor, compositions thereof, and methods of using the same.

Abstract: The present disclosure relates to the field of organic electroluminescence materials and particularly relates to a compound and an organic light emitting display device. The compound has a structure represented by Formula (I): and, m, n, p, q, r, s, u, and v are each independently selected from 0 or 1, at least one of r and s is 1, at least one of u and v is 1, L1, L2, L3, and L4 are each independently selected from substituted or unsubstituted C6-C40 aryl, or substituted or unsubstituted C3-C40 heterocyclyl, and A1, A2, A3, and A4 each are independently selected from an electron acceptor unit.

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to manufacturing transistors that include a substrate, an epitaxial layer with a first side and a second side opposite the first side, where the first side and the second side of the epitaxial layer are substantially planar, where the second side of the epitaxial layer is substantially parallel to the first side, and where the first side of the epitaxial layer is directly coupled with a side of the substrate. In particular, the epitaxial layer may be adjacent to an oxide layer having a side that is substantially planar, where the second side of the epitaxial layer is adjacent to the side of the oxide layer, and the epitaxial layer was grown and the growth was constrained by the oxide layer.

Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

Abstract: A method for training a chromosome recognition model includes: identifying objects on a karyotype image, obtaining a mask and a minimal bounding box of each of the chromosome objects, and obtaining an organized image that includes a set of organized chromosome objects; generating a simulated metaphase image in which the chromosome objects are randomly reorganized; detecting the plurality of chromosome objects on the simulated metaphase image; obtaining a recalibrated image in which the chromosome objects are separated from one another, so as to train the chromosome recognition model for identifying feature of chromosome objects included in an image.

Abstract: Certain aspects relate to systems and techniques for alignment and docking of robotic arm of a robotic system for surgery. In one aspect, the system includes a robotic arm, a drive mechanism attached to the robotic arm, and a cannula. The system may further include a first sensor coupled to either the robotic arm or the drive mechanism configured to direct automatic movement of the robotic arm towards the cannula, and a second sensor, that is different than the first sensor, coupled to either the robotic arm or the drive mechanism configured to direct manual movement of the robotic arm towards the cannula.

Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.

Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

Abstract: Disclosed herein are memory devices with a logic region between memory regions. For example, in some embodiments, a memory device may include: a first memory region; a second memory region; a logic region between the first memory region and the second memory region; and a metallization stack, wherein the first memory region is between the logic region and the metallization stack.

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

Abstract: A land grid array semiconductor device is disclosed which is configured for removable insertion to and from a host device. The land grid array semiconductor device may include a first set of one or more contact fingers on the first surface of the land grid array semiconductor device, and a second set of one or more contact fingers on the second surface of the land grid array semiconductor device. In order to electrically couple the second set of one or more contact fingers, one or more electrical connectors may be provided physically extending between the second set of one or more contact fingers and at least one of the substrate and the at least one semiconductor die.

Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.