Patents by Inventor Ying Huang

Ying Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11916118
    Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.
    Type: Grant
    Filed: April 4, 2023
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Ehren Mannebach, Aaron Lilak, Hui Jae Yoo, Patrick Morrow, Anh Phan, Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey
  • Patent number: 11916939
    Abstract: An abnormal traffic detection method is provided according to an embodiment of the disclosure. The method includes: obtaining network traffic data of a target device; sampling the network traffic data by a sampling window with a time length to obtain sampling data; generating, according to the sampling data, an image which presents a traffic feature of the network traffic data corresponding to the time length; and analyzing the image to generate evaluation information corresponding to an abnormal traffic. In addition, an abnormal traffic detection device is also provided according to an embodiment of the disclosure to improve a detection ability and/or an analysis ability for the abnormal traffic and/or a malware.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: February 27, 2024
    Assignee: Acer Cyber Security Incorporated
    Inventors: Ming-Kung Sun, Tsung-Yu Ho, Zong-Cyuan Jhang, Chiung-Ying Huang
  • Patent number: 11917452
    Abstract: Provided are an information transmission method and device. The method includes that: an Integrated Access and Backhaul Links (IAB) node transmits link information to a second IAB node, wherein the second IAB node is an IAB child node or an IAB parent node or an IAB donor. Also provided are an electronic device and a storage medium.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: February 27, 2024
    Assignee: ZTE CORPORATION
    Inventors: Ying Huang, Lin Chen
  • Publication number: 20240063234
    Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a substrate and a transfer gate disposed from a front-side surface of the substrate. The CMOS image sensor further comprises a photo detecting column disposed at one side of the transfer gate within the substrate. The photo detecting column comprises a doped sensing layer comprising one or more recessed portions along a circumference of the doped sensing layer in parallel to the front-side surface of the substrate. By forming the photo detecting column with recessed portions, a junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.
    Type: Application
    Filed: November 2, 2023
    Publication date: February 22, 2024
    Inventors: Chia-Yu Wei, Hsin-Chi Chen, Kuo-Cheng Lee, Ping-Hao Lin, Hsun-Ying Huang, Yen-Liang Lin, Yu Ting Kao
  • Publication number: 20240064715
    Abstract: A method of wireless communication is described. The method of wireless communication comprises receiving, by a first node of an integrated access and backhaul (IAB) network, resource information that includes resource availability information and/or resource configuration information; and transmitting, by the first node, the resource information to a second node.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 22, 2024
    Inventors: Ying HUANG, Lin CHEN
  • Patent number: 11903012
    Abstract: A method and apparatus for carrier aggregation is disclosed. In one embodiment, a method performed by a first wireless communication node, comprising: receiving a downlink signal containing first information from a second wireless communication node, and based on at least a portion of the first information, determining first resource information to perform sidelink communication between the first wireless communication node and at least one third wireless communication node.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: February 13, 2024
    Assignee: ZTE CORPORATION
    Inventors: Ying Huang, Lin Chen
  • Patent number: 11901739
    Abstract: A backup voltage and frequency support method for a 100%-renewable energy sending-end grid, including: (S1) selecting a plurality of support nodes in the 100%-renewable energy sending-end grid; (S2) mounting a backup voltage and frequency support device at each support node; and (S3) dynamically adjusting an active power output of a renewable energy station of the 100%-renewable energy sending-end grid according to a frequency of a grid-connection point.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: February 13, 2024
    Assignee: Zhejiang University
    Inventors: Zheren Zhang, Wentao Liu, Ying Huang, Yiyan Dong, Zheng Xu
  • Publication number: 20240047559
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a bottom-up oxidation approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxidized nanowires. A gate stack is over the vertical arrangement of nanowires and around the one or more oxidized nanowires.
    Type: Application
    Filed: October 19, 2023
    Publication date: February 8, 2024
    Inventors: Willy RACHMADY, Gilbert DEWEY, Jack T. KAVALIEROS, Aaron LILAK, Patrick MORROW, Anh PHAN, Cheng-Ying HUANG, Ehren MANNEBACH
  • Patent number: 11891678
    Abstract: The present disclosure provides a method for optimizing a liquid injection process of ionic rare earth ore, including the following steps of: 1) testing the hydraulic properties of an ore body; 2) determining the diffusion degree of the ore body; 3) determining the spatial distribution of the rare earth grade and the impurity grade of the ore body prior to leaching; 4) determining model parameters of competitive exchange of rare earth ions and impurity ions with ammonium ions; 5) obtaining distribution of rare earth ion concentration within the ore body after completion of leaching; 6) obtaining a profile plot of a rare earth leaching rate as a function of the concentration and dosage of an injected leaching agent; and 7) determining a minimum leaching agent dosage to achieve a target leaching rate according to the profile plot, and then determining the ammonium sulfate concentration according to the minimum leaching agent dosage.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: February 6, 2024
    Assignees: JIANGXI UNIVERSITY OF SCIENCE AND TECHNOLOGY, LONGYAN RARE-EARTH DEVELOPMENT CO., LTD.
    Inventors: Guanshi Wang, Ping Long, Wenli Liu, Ying Huang, Dingshun He, Lei Qin, Shili Hu, Chenliang Peng, Sihai Luo, Guoqiang Deng
  • Patent number: 11894372
    Abstract: A device is disclosed. The device includes a first semiconductor fin, a first source-drain epitaxial region adjacent a first portion of the first semiconductor fin, a second source-drain epitaxial region adjacent a second portion of the first semiconductor fin, a first gate conductor above the first semiconductor fin, a gate spacer covering the sides of the gate conductor, a second semiconductor fin below the first semiconductor fin, a second gate conductor on a first side of the second semiconductor fin and a third gate conductor on a second side of the second semiconductor fin, a third source-drain epitaxial region adjacent a first portion of the second semiconductor fin, and a fourth source-drain epitaxial region adjacent a second portion of the second semiconductor fin. The device also includes a dielectric isolation structure below the first semiconductor fin and above the second semiconductor fin that separates the first semiconductor fin and the second semiconductor fin.
    Type: Grant
    Filed: January 11, 2023
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Cheng-Ying Huang, Gilbert Dewey, Aaron Lilak, Patrick Morrow, Anh Phan, Ehren Mannebach, Jack T. Kavalieros
  • Publication number: 20240038804
    Abstract: An image sensor device is provided. The image sensor device includes a substrate having a front surface, a back surface, and a light-sensing region. The image sensor device includes a first isolation structure extending from the front surface into the substrate. The first isolation structure surrounds a first portion of the light-sensing region, the first isolation structure has an etch stop layer, the etch stop layer has an end portion, and the end portion has an H-like shape. The image sensor device includes a second isolation structure extending into the substrate from the back surface to the end portion. The second isolation structure surrounds a second portion of the light-sensing region.
    Type: Application
    Filed: October 16, 2023
    Publication date: February 1, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yun-Wei CHENG, Chun-Hao CHOU, Kuo-Cheng LEE, Hsun-Ying HUANG
  • Patent number: 11887988
    Abstract: Thin film transistor structures may include a regrown source or drain material between a channel material and source or drain contact metallization. The source or drain material may be selectively deposited at low temperatures to backfill recesses formed in the channel material. Electrically active dopant impurities may be introduced in-situ during deposition of the source or drain material. The source or drain material may overlap a portion of a gate electrode undercut by the recesses. With channel material of a first composition and source or drain material of a second composition, thin film transistor structures may display low external resistance and high channel mobility.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: January 30, 2024
    Assignee: Intel Corporation
    Inventors: Ashish Agrawal, Jack Kavalieros, Anand Murthy, Gilbert Dewey, Matthew Metz, Willy Rachmady, Cheng-Ying Huang, Cory Bomberger
  • Publication number: 20240030921
    Abstract: A method of generating an integrated circuit (IC) layout diagram includes arranging a first portion of first through fourth pluralities of active regions and a plurality of gate regions of a cell as a functional circuit in a first portion of the cell, arranging a second portion of the first through fourth pluralities of active regions and the plurality of gate regions of the cell as a one of a decoupling capacitor or an antenna diode in a second portion of the cell, and storing an IC layout diagram of the cell in a storage device.
    Type: Application
    Filed: October 6, 2023
    Publication date: January 25, 2024
    Inventors: Ying HUANG, Changlin HUANG, Jing DING, Qingchao MENG
  • Publication number: 20240031880
    Abstract: Methods, systems, and devices for integrated access and backhaul (IAB) donor migration in mobile and cellular networks are described. An example method for wireless communication includes transmitting, by a first IAB donor to a second IAB donor, an Xn Application Protocol (XnAP) message comprising an Internet Protocol (IP) address request information, and receiving, from the second IAB donor, an IP address information. Another example method for wireless communication includes transmitting, by a first network node to a second network node, a message comprising a transmission action indicator information, wherein the transmission action indicator information configures the second network node to perform one or more transmission actions to a wireless device.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 25, 2024
    Inventors: Ying HUANG, Lin CHEN
  • Publication number: 20240021645
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip structure. The method includes forming a first dielectric bonding layer over a first dielectric structure, which is disposed on a first substrate and surrounds a first plurality of interconnects. The first dielectric bonding layer is patterned to form a first recess exposing one of the first plurality of interconnects. A first conductive bonding segment is formed within the first recess. A second dielectric bonding layer is formed over a TSV extending through a second substrate. The second dielectric bonding layer is patterned to form a second recess exposing the TSV. A second conductive bonding segment is formed within the second recess. The first substrate is bonded to the second substrate along an interface comprising dielectric and conductive regions. The conductive region includes a conductive interface between the first and second conductive bonding segments.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 18, 2024
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang, Wei-Chih Weng, Yu-Yang Shen
  • Patent number: 11865684
    Abstract: A pneumatic electric nail gun includes a muzzle unit, a striking cylinder that is connected to the muzzle unit, a piston rod subunit that extends movably from the striking cylinder into the muzzle unit, an electric unit that drives movement of the piston rod subunit from a standby position to a nail-striking position for striking a nail, and a connecting unit that includes a plurality of fasteners and a plurality of buffer members. The fasteners extend through the electric unit and secure the electric unit to the muzzle unit. Each of the buffer members surrounds a respective one of the fasteners and fills a space between the respective one of the fasteners, the electric unit and the muzzle unit for shock absorption during a nail-striking process.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: January 9, 2024
    Assignee: Basso Industry Corp.
    Inventors: An-Gi Liu, Chang-Sheng Lin, Fu-Ying Huang
  • Publication number: 20240006499
    Abstract: An integrated circuit includes an upper semiconductor body extending in a first direction from an upper source region to an upper drain region, and a lower semiconductor body extending in the first direction from a lower source region to a lower drain region. The upper body is spaced vertically from the lower body in a second direction orthogonal to the first direction. A gate spacer structure is adjacent to the upper and lower source regions. In an example, the gate spacer structure includes (i) a first section having a first dimension in the first direction, and (ii) a second section having a second dimension in the first direction. In an example, the first dimension is different from the second dimension by at least 1 nm. In some cases, an intermediate portion of the gate spacer structure extends laterally within a given gate structure, or between upper and lower gate structures.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Cheng-Ying Huang, Kai Loon Cheong, Pooja Nath, Susmita Ghose, Rambert Nahm, Natalie Briggs, Charles C. Kuo, Nicole K. Thomas, Munzarin F. Qayyum, Marko Radosavljevic, Jack T. Kavalieros, Thoe Michaelos, David Kohen
  • Patent number: 11862715
    Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: January 2, 2024
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Jack Kavalieros, Ian Young, Matthew Metz, Willy Rachmady, Uygar Avci, Ashish Agrawal, Benjamin Chu-Kung
  • Patent number: D1014543
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 13, 2024
    Assignee: MEDICALTEK CO., LTD.
    Inventors: Yen-Yu Wang, Chieh-Chu Chen, Jing-Ying Huang
  • Patent number: D1015362
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: February 20, 2024
    Assignee: MEDICALTEK CO., LTD.
    Inventors: Yen-Yu Wang, Chieh-Chu Chen, Jing-Ying Huang