Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

Abstract: An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.

Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.

Abstract: A compound of Formula (I), or a pharmaceutically acceptable salt thereof, is provided that has been shown to be useful for treating a PRC2-mediated disease or disorder: wherein R1, R2, R3, R4, R5, and n are as defined herein.

Abstract: Multiple non-silicon semiconductor material layers may be stacked within a fin structure. The multiple non-silicon semiconductor material layers may include one or more layers that are suitable for P-type transistors. The multiple non-silicon semiconductor material layers may further include one or more one or more layers that are suited for N-type transistors. The multiple non-silicon semiconductor material layers may further include one or more intervening layers separating the N-type from the P-type layers. The intervening layers may be at least partially sacrificial, for example to allow one or more of a gate, source, or drain to wrap completely around a channel region of one or more of the N-type and P-type transistors.

Abstract: A device includes a first buried layer over a substrate, a second buried layer over the first buried layer, a first well over the first buried layer and the second buried layer, a first high voltage well, a second high voltage well and a third high voltage well extending through the first well, wherein the second high voltage well is between the first high voltage well and the third high voltage well, a first drain/source region in the first high voltage well, a first gate electrode over the first well, a second drain/source region in the second high voltage well and a first isolation region in the second high voltage well, and between the second drain/source region and the first gate electrode, wherein a bottom of the first isolation region is lower than a bottom of the second drain/source region.

Abstract: A semiconductor structure includes a first gate structure, a second gate structure coupled to the first gate structure, a source region, a first drain region, and a second drain region. The source region is surrounded by the first gate structure and the second gate structure. The first drain region is separated from the source region by the first gate structure. The second drain region is separated from the source region by the second gat structure. A shape of the first drain region and a shape of the second drain region are different from each other from a plan view.

Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a shallow trench isolation, and a color filter layer. The radiation sensing member is in the semiconductor substrate. An interface between the radiation sensing member and the semiconductor substrate includes a direct band gap material. The shallow trench isolation is in the semiconductor substrate and surrounds the radiation sensing member. The color filter layer covers the radiation sensing member.

Abstract: A device array substrate is provided and includes a flexible base, a pixel island, and a connection line. The pixel island is disposed on the flexible base, and at least one edge of the pixel island is provided with at least one opening. The connection line enters the pixel island via the opening. A display device is also provided and includes the device array substrate.

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.

Abstract: An integrated circuit includes a first terminal-conductor, a second terminal-conductor, and a gate-conductor between the first terminal-conductor and the second terminal-conductor. The first terminal-conductor intersects both an active-region structure and a power rail. The second terminal-conductor intersects the active-region structure without intersecting the power rail. The gate-conductor intersects the active-region structure and is adjacent to the first terminal-conductor and the second terminal-conductor. A first width of the first terminal-conductor is larger than a second width of the second terminal-conductor by a predetermined amount.

Abstract: The disclosure provides an electronic device, including a circuit board, multiple semiconductor components, a first light reflecting structure, and a second light reflecting structure. The circuit board includes a substrate, and the substrate may have a first surface and at least one side surface. The multiple semiconductor components are disposed on the first surface. The first light reflecting structure is disposed on the first surface. The second light reflecting structure is disposed on the first surface and the at least one side surface.

Abstract: The present invention relates to novel use of koumine, an alkaloid monomer from Gelsemium elegans Benth., or a pharmaceutically acceptable salt thereof, and more particularly to use of koumine or its pharmaceutically acceptable salt in the preparation of a medicament for the treatment of inflammatory bowel disease.

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

Abstract: Sidelink based relay communications include communications through a relay user equipment (“UE”) between a basestation and a remote UE. Relay communications can be improved by addressing incompatibilities between different devices, which support different features/operations, such as the layers of communication. Access control and an establishment cause value can also be addressed by the relay communications. Paging identification and system information can be communicated by relay communications, such as through the relay UE to improve communications.

Abstract: A technique for providing search results may include determining a first entity type, a second entity type, and a relationship type based on a compositional query. The technique may also include identifying nodes of a knowledge graph corresponding to entity references of the first entity type and entity references of the second entity type. The technique may also include determining from the knowledge graph an attribute value corresponding to the relationship type for each entity reference of the first entity type and for each entity reference of the second entity type. The technique may also include comparing the attribute value of each entity reference of the first entity type with the attribute value of each entity reference of the second entity type. The technique may also include determining one or more resultant entity references from the entity references of the first entity type based on the comparing.

Abstract: Provided is a method for performing relay forwarding on integrated access and backhaul (IAB) links. The method includes receiving, by a first IAB node, a data packet; and transmitting, by the first IAB node, the data packet to an IAB donor. Further provided are an information acquisition method, an IAB node, an IAB donor node and a storage medium.

Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).