Abstract: A slurry dispensing unit for a chemical mechanical polishing (CMP) apparatus is provided. The slurry dispensing unit includes a nozzle, a mixer, a first fluid source, and a second fluid source. The nozzle is configured to dispense a slurry. The mixer is disposed upstream of the nozzle. The first fluid source is connected to the mixer through a first pipe and configured to provide a first fluid including a first component of the slurry. The second fluid source is connected to the mixer through a second pipe and configured to provide a second fluid including a second component of the slurry, wherein the second component is different from the first component.

Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.

Abstract: A method includes forming a flowable dielectric layer in a trench of a substrate; curing the flowable dielectric layer; and annealing the cured flowable dielectric layer to form an insulation structure and a liner layer. The insulation structure is formed in the trench, the liner layer is formed between the insulation structure and the substrate, and the liner layer includes nitrogen.

Abstract: A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer, removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A block layer is deposited over the metal layer using Atomic Layer Deposition (ALD). The remaining portion of the recess is filled with metallic materials, wherein the metallic materials are overlying the metal layer.

Abstract: In an embodiment, a method includes: performing a self-limiting process to modify a top surface of a wafer; after the self-limiting process completes, removing the modified top surface from the wafer; and repeating the performing the self-limiting process and the removing the modified top surface from the wafer until a thickness of the wafer is decreased to a predetermined thickness.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: An apparatus includes a first metrology tool configured to measure an initial thickness of a wafer. The apparatus includes a controller connected to the first metrology tool and configured to calculate a polishing time based on a material removal rate, a predetermined thickness and the initial thickness of the wafer. The apparatus includes a polishing tool connected to the controller and configured to polish the wafer for a first duration equal to the polishing time. The apparatus includes a second metrology tool connected to the controller and configured to measure a polished thickness. The controller is configured for receiving the initial thickness from the first metrology tool and the polished thickness from the second metrology tool, updating the material removal rate based on the predetermined thickness, the polishing time and the polished thickness, and calculating an etching time for etching the polished wafer using the polished thickness.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: A wafer thinning apparatus includes a first metrology tool configured to measure an initial thickness of the wafer. The wafer thinning apparatus further includes a controller connected to the first metrology tool, and configured to determine a polishing time based on the initial thickness, a predetermined thickness and a material removal rate. The wafer thinning apparatus further includes a polishing tool connected to the controller configured to polish the wafer for a period of time equal to the polishing time. The wafer thinning apparatus includes a second metrology tool connected to the controller and the polishing tool, and configured to measure a polished thickness. The controller is configured to update the material removal rate based on the polished thickness, the predetermined thickness and the polishing time.

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a resistive random access memory (RRAM) device. The method includes forming one or more bottom electrode films over a lower interconnect layer within a lower inter-level dielectric layer. A data storage film having a variable resistance is formed above the one or more bottom electrode films. A lower top electrode film including a metal is over the data storage film, one or more oxygen barrier films are over the lower top electrode film, and an upper top electrode film including a metal nitride is formed over the one or more oxygen barrier films The one or more oxygen barrier films include one or more of a metal oxide film and a metal oxynitride film. The upper top electrode film is formed to be completely confined over a top surface of the one or more oxygen barrier films.

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, first spacers, second spacers and source and drain regions is described. The substrate has fins and insulators disposed between the fins. The at least one gate structure is disposed over the fins and disposed on the insulators. The first spacers are disposed on opposite sidewalls of the at least one gate structure. The source and drain regions are disposed on two opposite sides of the at least one gate structure and beside the first spacers. The second spacers are disposed on the two opposite sides of the at least one gate structure and beside the first spacers. The source and drain regions are sandwiched between the opposite second spacers.

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a bottom electrode that is disposed over a lower interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A data storage structure is arranged over the bottom electrode and a multi-layer top electrode is disposed over the data storage structure. The multi-layer top electrode includes conductive top electrode layers separated by an oxygen barrier structure that is configured to mitigate movement of oxygen between the conductive top electrode layers. A sidewall spacer is disposed directly over the bottom electrode and has a sidewall that covers outermost sidewalls of the conductive top electrode layers and the oxygen barrier structure.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: Various embodiments provide a thickness sensor and method for measuring a thickness of discrete conductive features, such as conductive lines and plugs. In one embodiment, the thickness sensor generates an Eddy current in a plurality of discrete conductive features, and measures the generated Eddy current generated in the discrete conductive features. The thickness sensor has a small sensor spot size, and amplifies peaks and valleys of the measured Eddy current. The thickness sensor determines a thickness of the discrete conductive features based on a difference between a minimum amplitude value and a maximum amplitude value of the measured Eddy current.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device has a bottom electrode disposed over a lower interconnect layer surrounded by an inter-level dielectric (ILD) layer. A dielectric data storage layer having a variable resistance is located above the bottom electrode, and a multi-layer top electrode is disposed over the dielectric data storage layer. The multi-layer top electrode has conductive top electrode layers separated by an oxygen barrier structure configured to mitigate movement of oxygen within the multi-layer top electrode. By including an oxygen barrier structure within the top electrode, the reliability of the RRAM device is improved since oxygen is kept close to the dielectric data storage layer.

Abstract: A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.