Patents by Inventor Ying-Lang Wang

Ying-Lang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10516048
    Abstract: A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Chih Chen, Ying-Lang Wang, Chih-Mu Huang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
  • Publication number: 20190385909
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Application
    Filed: August 30, 2019
    Publication date: December 19, 2019
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Patent number: 10510891
    Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Chun-Hung Wu, Chia-Cheng Chen, Liang-Yin Chen, Huicheng Chang, Ying-Lang Wang
  • Publication number: 20190378928
    Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.
    Type: Application
    Filed: July 8, 2019
    Publication date: December 12, 2019
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Chun-Hung Wu, Chia-Cheng Chen, Liang-Yin Chen, Huicheng Chang, Ying-Lang Wang
  • Publication number: 20190371664
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Publication number: 20190252427
    Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Ching-Yao Sun, Jyun-Ru Wu, Ching-Che Huang, Szu-An Wu, Ying-Lang Wang
  • Publication number: 20190224810
    Abstract: A polishing pad includes a pad layer and one or more polishing structures over an upper surface of the pad layer, where each of the one or more polishing structures has a pre-determined shape and is formed at a pre-determined location of the pad layer, where the one or more polishing structures comprise at least one continuous line shaped segment extending along the upper surface of the pad layer, where each of the one or more polishing structures is a homogeneous material.
    Type: Application
    Filed: July 2, 2018
    Publication date: July 25, 2019
    Inventors: Chih Hung Chen, Kei-Wei Chen, Ying-Lang Wang
  • Patent number: 10347762
    Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Chun-Hung Wu, Chia-Cheng Chen, Liang-Yin Chen, Huicheng Chang, Ying-Lang Wang
  • Patent number: 10283702
    Abstract: Methods for a resistive random access memory (RRAM) device are disclosed. A bottom electrode is formed over a substrate. A top electrode is formed over the bottom electrode. A resistive switching layer is formed interposed between the top electrode and the bottom electrode. The resistive switching is made of a composite of a metal, Si, and O, formed by oxidation of a metal silicide of a metal, co-deposition of the metal and silicon in oxygen ambiance, co-deposition of a metal oxide of the metal and silicon, or co-deposition of a metal oxide of the metal and silicon oxide. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Chang Chang, Yong-En Syu, Fu-Yen Jian, Shih-Chieh Chang, Ying-Lang Wang
  • Patent number: 10276621
    Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Ching-Yao Sun, Jyun-Ru Wu, Ching-Che Huang, Szu-An Wu, Ying-Lang Wang
  • Publication number: 20180375024
    Abstract: The present disclosure relates to an RRAM device having an electrode with an oxygen barrier structure, which is configured to improve RRAM reliability by mitigating oxygen movement and thereby maintaining oxygen within close proximity of a dielectric data storage layer, and an associated method of formation. In some embodiments, the RRAM device has a bottom electrode disposed over a lower interconnect layer surrounded by a ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom electrode, and a multi-layer top electrode disposed over the dielectric data storage layer. The multi-layer top electrode has conductive top electrode layers separated by an oxygen barrier structure configured to mitigate movement of oxygen within the multi-layer top electrode. By including an oxygen barrier structure within the top electrode, the reliability of the RRAM device is improved since oxygen is kept close to the dielectric data storage layer.
    Type: Application
    Filed: March 29, 2018
    Publication date: December 27, 2018
    Inventors: Wen-Ting Chu, Tong-Chern Ong, Ying-Lang Wang
  • Publication number: 20180337113
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a gate structure separating source and drain (S/D) features. The semiconductor device further includes a first dielectric layer formed over the substrate, the first dielectric layer including a first interconnect structure in electrical contact with the S/D features. The semiconductor device further includes an intermediate layer formed over the first dielectric layer, the intermediate layer having a top surface that is substantially coplanar with a top surface of the first interconnect structure. The semiconductor device further includes a second dielectric layer formed over the intermediate layer, the second dielectric layer including a second interconnect structure in electrical contact with the first interconnect structure and a third interconnect structure in electrical contact with the gate structure.
    Type: Application
    Filed: July 27, 2018
    Publication date: November 22, 2018
    Inventors: Jeng Min Liang, Ying-Lang Wang, Kei-Wei Chen, Chi-Wen Liu, Kuo-Hsiu Wei, Kuo-Feng Huang
  • Patent number: 10096672
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Chih Chen, Chih-Mu Huang, Fu-Tsun Tsai, Meng-Yi Wu, Yung-Fa Lee, Ying-Lang Wang
  • Publication number: 20180281152
    Abstract: A slurry dispensing unit for a chemical mechanical polishing (CMP) apparatus is provided. The slurry dispensing unit includes a nozzle, a mixer, a first fluid source, and a second fluid source. The nozzle is configured to dispense a slurry. The mixer is disposed upstream of the nozzle. The first fluid source is connected to the mixer through a first pipe and configured to provide a first fluid including a first component of the slurry. The second fluid source is connected to the mixer through a second pipe and configured to provide a second fluid including a second component of the slurry, wherein the second component is different from the first component.
    Type: Application
    Filed: July 11, 2017
    Publication date: October 4, 2018
    Inventors: Kei-Wei CHEN, Chih-Hung CHEN, Ying-Lang WANG
  • Publication number: 20180269307
    Abstract: In an embodiment, a method includes: performing a self-limiting process to modify a top surface of a wafer; after the self-limiting process completes, removing the modified top surface from the wafer; and repeating the performing the self-limiting process and the removing the modified top surface from the wafer until a thickness of the wafer is decreased to a predetermined thickness.
    Type: Application
    Filed: January 19, 2018
    Publication date: September 20, 2018
    Inventors: Chih Hung Chen, Kei-Wei Chen, Ying-Lang Wang
  • Patent number: 10058974
    Abstract: A method for performing a CMP process is provided. The method includes performing the CMP process. The method further includes during the CMP process detecting a motion of a carrier head about a rotation axis beside a polishing pad. The method also includes producing a control signal corresponding to a detected result of the motion. In addition, the method includes prohibiting the rotation of the carrier head about a rotation axis by a driving motor which is controlled by the control signal. And, the method includes selecting a point of time at which the CMP process is terminated after the control signal is substantially the same as a threshold value.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 28, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chih-Hung Chen, Kei-Wei Chen, Ying-Lang Wang
  • Publication number: 20180151667
    Abstract: A method includes forming a flowable dielectric layer in a trench of a substrate; curing the flowable dielectric layer; and annealing the cured flowable dielectric layer to form an insulation structure and a liner layer. The insulation structure is formed in the trench, the liner layer is formed between the insulation structure and the substrate, and the liner layer includes nitrogen.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 31, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Ming LIN, Shiu-Ko JANGJIAN, Chun-Che LIN, Ying-Lang WANG, Wei-Ken LIN, Chuan-Pu LIU
  • Publication number: 20180108836
    Abstract: Methods for a resistive random access memory (RRAM) device are disclosed. A bottom electrode is formed over a substrate. A top electrode is formed over the bottom electrode. A resistive switching layer is formed interposed between the top electrode and the bottom electrode. The resistive switching is made of a composite of a metal, Si, and O, formed by oxidation of a metal silicide of a metal, co-deposition of the metal and silicon in oxygen ambiance, co-deposition of a metal oxide of the metal and silicon, or co-deposition of a metal oxide of the metal and silicon oxide. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.
    Type: Application
    Filed: December 18, 2017
    Publication date: April 19, 2018
    Inventors: Ting-Chang Chang, Yong-En Syu, Fu-Yen Jian, Shih-Chieh Chang, Ying-Lang Wang
  • Patent number: 9931726
    Abstract: A wafer edge trimming tool includes an abrasive tape and a holding module configured to hold the abrasive tape against portions of an edge of a rotating wafer during a wafer edge trimming process.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Huai-Tei Yang, Ying-Lang Wang
  • Publication number: 20180061987
    Abstract: A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.
    Type: Application
    Filed: November 6, 2017
    Publication date: March 1, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: I-Chih CHEN, Ying-Lang WANG, Chih-Mu HUANG, Ying-Hao CHEN, Wen-Chang KUO, Jung-Chi JENG