Patents by Inventor Ying-Lang Wang

Ying-Lang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9570311
    Abstract: Methods of thinning a plurality of semiconductor wafers and apparatuses for carrying out the same are disclosed. A grinding module within a set of grinding modules receives and grinds a semiconductor wafer. A polishing module receives the semiconductor wafer from the grinding module and polishes the wafer. The polishing module is configured to polish the semiconductor wafer in less time than the grinding module is configured to grind the corresponding wafer.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: February 14, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Ting Kuo, Kei-Wei Chen, Ying-Lang Wang, Kuo-Hsiu Wei
  • Publication number: 20170033179
    Abstract: A trench structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The substrate has a trench therein. The isolation structure is disposed in the trench. The liner layer is disposed between the substrate and the isolation structure. The liner layer includes nitrogen, and the liner layer has spatially various nitrogen concentration.
    Type: Application
    Filed: July 29, 2015
    Publication date: February 2, 2017
    Inventors: Jia-Ming LIN, Shiu-Ko JANGJIAN, Chun-Che LIN, Ying-Lang WANG, Wei-Ken LIN, Chuan-Pu LIU
  • Patent number: 9520477
    Abstract: A semiconductor device includes a substrate, a first and second source/drain regions, and a gate stack. The first and second source/drain regions are disposed on the substrate. The gate stack is disposed over the substrate to overlay a channel region between the first and second S/D regions. The gate stack includes a gate dielectric layer disposed over the substrate; and a metal alloy disposed on the gate dielectric layer and configured as a filling layer in the gate stack; wherein the metal alloy has a first corrosion resistance corresponding to an etchant designed for removing a carbon-containing polymer.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: December 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chi-Cheng Hung, Yu-Sheng Wang, Kei-Wei Chen, Ying-Lang Wang
  • Patent number: 9502647
    Abstract: A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a resistance-switching network disposed between the pair of electrodes. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer. The group-IV doping layer comprises silicon oxide doped with a group-IV element. The porous low-k layer comprises porous silicon oxide or porous hafnium oxide. The group-IV element may comprise zirconium, titanium, or hafnium. The porous low-k layer may be prepared by inductively coupled plasma (ICP) treatment. A method of fabricating a resistive memory is disclosed. The method comprises forming a resistance-switching network on a first electrode using sputtering and forming a second electrode on the resistance-switching network using sputtering. The resistance-switching network comprises a group-IV element doping layer and a porous low-k layer.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Chih-Hung Pan, Ying-Lang Wang, Kei-Wei Chen, Shih-Chieh Chang, Te-Ming Kung
  • Patent number: 9502290
    Abstract: A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing a plasma process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Sheng Wang, Shih-Ho Lin, Kei-Wei Chen, Szu-An Wu, Ying-Lang Wang
  • Patent number: 9490345
    Abstract: A semiconductor device includes a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; and an interconnect plug on the doped region. The raised source/drain region includes a top surface being elevated from a surface of the substrate; and a doped region exposed on the top surface. The doped region includes a dopant concentration greater than any other portions of the raised source/drain region. A bottommost portion of the interconnect plug includes a width approximate to a width of the doped region.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: November 8, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Chih Chen, Fu-Tsun Tsai, Yung-Fa Lee, Ko-Min Lin, Chih-Mu Huang, Ying-Lang Wang
  • Publication number: 20160300906
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.
    Type: Application
    Filed: April 7, 2015
    Publication date: October 13, 2016
    Inventors: I-Chih CHEN, Chih-Mu HUANG, Fu-Tsun TSAI, Meng-Yi WU, Yung-Fa LEE, Ying-Lang WANG
  • Publication number: 20160276456
    Abstract: A semiconductor device includes a substrate, a first and second source/drain regions, and a gate stack. The first and second source/drain regions are disposed on the substrate. The gate stack is disposed over the substrate to overlay a channel region between the first and second S/D regions. The gate stack includes a gate dielectric layer disposed over the substrate; and a metal alloy disposed on the gate dielectric layer and configured as a filling layer in the gate stack; wherein the metal alloy has a first corrosion resistance corresponding to an etchant designed for removing a carbon-containing polymer.
    Type: Application
    Filed: March 16, 2015
    Publication date: September 22, 2016
    Inventors: CHI-CHENG HUNG, YU-SHENG WANG, KEI-WEI CHEN, YING-LANG WANG
  • Patent number: 9419155
    Abstract: This description relates to a sensing product formed using a substrate with a plurality of epi-layers. At least a first epi-layer has a different composition than the composition of a second epi-layer. The sensing product optionally includes at least one radiation sensing element in the second epi-layer and optionally an interconnect structure over the second epi-layer. The sensing product is formed by removing the substrate and all epi-layers other than the second epi-layer. A light incident surface of the second epi-layer has a total thickness variation of less than about 0.15 ?m.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chieh Chang, Yu-Ku Lin, Ying-Lang Wang
  • Patent number: 9379275
    Abstract: A method for reducing dark current in image sensors comprises providing a backside illuminated image sensor wafer, depositing a first passivation layer on a backside of the backside illuminated image sensor wafer, depositing a plasma enhanced passivation layer on the first passivation layer and depositing a second passivation layer on the plasma enhanced passivation layer.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Miao-Cheng Liao, Jinn-Kwei Liang, Wen-Chieh Hsieh, Shiu-Ko JangJian, Hsiang Hsiang Ko, Ying-Lang Wang
  • Publication number: 20160181427
    Abstract: A semiconductor device includes an isolation feature in a substrate. The semiconductor device further includes a first source/drain feature in the substrate, wherein a first side of the first source/drain feature contacts the isolation feature, and the first source/drain feature exposes a portion of the isolation feature below a top surface of the substrate. The semiconductor device further includes a silicide layer over the first source/drain feature. The semiconductor device further includes a dielectric layer along the exposed portion of the isolation feature below the top surface of the substrate, wherein the dielectric layer contacts the silicide layer. The semiconductor device further includes a second source/drain feature in the substrate on an opposite side of a gate stack from the first source/drain feature, wherein the second source/drain feature has a substantially uniform thickness.
    Type: Application
    Filed: March 2, 2016
    Publication date: June 23, 2016
    Inventors: Wen Chu HSIAO, Lai Wan CHONG, Chun-Chieh WANG, Ying Min CHOU, Hsiang Hsiang KO, Ying-Lang WANG
  • Patent number: 9368394
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a semiconductor substrate; forming a conductive region at least partially in the semiconductor substrate; forming a dielectric layer over the substrate; forming a hard mask over the dielectric layer, the hard mask having an opening over the conductive region; dry etching the dielectric layer by a first etching gas to form a recessed feature, wherein a surface of the conductive region is therefore exposed at a bottom of the recessed feature, and a byproduct film is formed at an inner surface of the recessed feature; and dry etching the dielectric layer by a second etching gas, wherein the second etching gas chemically reacts with the byproduct film and the conductive region, and a sacrificial layer is therefore built up around the bottom of the recessed feature.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: June 14, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Li Hung, Te-Ming Kung, Chih-Hao Chen, Kei-Wei Chen, Ying-Lang Wang, Hung Jui Chang, Horng-Huei Tseng
  • Patent number: 9356059
    Abstract: A device includes semiconductor substrate having a front side and a backside. A polysilicon layer is disposed on the backside of the semiconductor substrate. The polysilicon layer includes a portion doped with a p-type impurity. A dielectric layer is disposed on the backside of the semiconductor substrate, wherein the polysilicon layer is between the semiconductor substrate and the polysilicon layer.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Kei-Wei Chen, Ying-Lang Wang
  • Publication number: 20160148967
    Abstract: A bonding pad structure comprises an interconnect layer, an isolation layer over the interconnect layer, a conductive pad, and one or more non-conducting stress-releasing structures. The conductive pad comprises a planar portion over the isolation layer, and one or more bridging portions extending through at least the isolation layer and to the interconnect layer for establishing electric contact therewith, wherein there is a trench in the one or more bridging portions. The one or more non-conducting stress-releasing structures are disposed between the isolation layer and the conductive pad. The trench is surrounded by one of the one or more non-conducting stress-releasing structures from a top view.
    Type: Application
    Filed: February 1, 2016
    Publication date: May 26, 2016
    Inventors: Volume Chien, I-Chih Chen, Hsin-Chi Chen, Hung-Ta Huang, Ying-Hao Chen, Ying-Lang Wang
  • Patent number: 9339912
    Abstract: An embodiment wafer polishing tool includes an abrasive tape, a polish head holding the abrasive tape, and a rotation module. The rotation module is configured to rotate a wafer during a wafer polishing process, and the polish head is configured to apply pressure to the abrasive tape toward a first surface of the wafer during the wafer polishing process.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Wei-Jen Lo, Ying-Lang Wang
  • Publication number: 20160114460
    Abstract: A method for making a conditioner disk used in a chemical mechanical polishing (CMP) process comprises applying a first layer of at least one binder over a substrate; disposing a plurality of diamond particles on the first layer of the at least one first binder at the plurality of locations; and fixing the plurality of diamond particles to the substrate by heating the substrate to a raised temperature and then cooling the substrate. The plurality of diamond particles disposed over the substrate are configured to provide a working diamond ratio higher than 50% when the conditioner disk is used in a CMP process.
    Type: Application
    Filed: January 5, 2016
    Publication date: April 28, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chang CHAO, Kei-Wei CHEN, Ying-Lang WANG
  • Publication number: 20160118434
    Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 28, 2016
    Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Ching-Yao Sun, Jyun-Ru Wu, Ching-Che Huang, Szu-An Wu, Ying-Lang Wang
  • Patent number: 9324863
    Abstract: A semiconductor device includes a source/drain feature in a substrate. The source/drain feature has an upper portion and a lower portion, the upper portion having a lower concentration of Ge than the lower portion. A Si-containing layer over the source/drain feature includes a metal silicide layer.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: April 26, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen Chu Hsiao, Lai Wan Chong, Chun-Chieh Wang, Ying Min Chou, Hsiang Hsiang Ko, Ying-Lang Wang
  • Patent number: 9281475
    Abstract: A resistive memory cell is disclosed. The resistive memory cell comprises a pair of electrodes and a multi-layer resistance-switching network disposed between the pair of electrodes. The multi-layer resistance-switching network comprises a pair of carbon doping layers and a group-IV element doping layer disposed between the pair of carbon doping layers. Each carbon doping layer comprises silicon oxide doped with carbon. The group-IV doping layer comprises silicon oxide doped with a group-IV element. A method of fabricating a resistive memory cell is also disclosed. The method comprises forming a first carbon doping layer on a first electrode using sputtering, forming a group-IV element doping layer on the first carbon doping layer using sputtering, forming a second carbon doping layer on the group-IV element doping layer using sputtering, and forming a second electrode on the second carbon doping layer using sputtering.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ting-Chang Chang, Kuan-Chang Chang, Tsung-Ming Tsai, Chih-Hung Pan, Ying-Lang Wang, Kei-Wei Chen, Shih-Chieh Chang, Te-Ming Kung
  • Patent number: 9254548
    Abstract: A method for making a conditioner disk used in a chemical mechanical polishing (CMP) process comprises applying a first layer of at least one binder over a substrate; disposing a plurality of diamond particles on the first layer of the at least one first binder at the plurality of locations; and fixing the plurality of diamond particles to the substrate by heating the substrate to a raised temperature and then cooling the substrate. The plurality of diamond particles disposed over the substrate are configured to provide a working diamond ratio higher than 50% when the conditioner disk is used in a CMP process.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Chang Chao, Kei-Wei Chen, Ying-Lang Wang