Patents by Inventor Ying Luo

Ying Luo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • EFFICIENT LOW-COMPLEXITY VIDEO COMPRESSION
    Publication number: 20160295234
    Abstract: Disclosed is a low-complexity and yet efficient lossy method to compress distortion information for motion estimation, resulting in significant reduction in needed storage capacity. A system for implementing the method and a computer-readable medium for storing the method are also disclosed. The method includes determining and storing a distortion value for each trial motion vector in a plurality of trial motion vectors. Each trial motion vector specifies a position of a search region relative to a reference frame. The method further includes compressing each of the distortion values as a fixed number of bits based upon a minimum distortion value amongst the stored distortion values, and re-storing each compressed distortion value in place of its uncompressed value.
    Type: Application
    Filed: April 6, 2015
    Publication date: October 6, 2016
    Applicant: ATI TECHNOLOGIES ULC
    Inventors: Khaled Mammou, Ihab M. A. Amer, Gabor Sines, John-Paul A. Compagnone, Gerald SC. Chan, Ying Luo, Edward A. Harold, Lei Zhang, Benedict Chien
  • Laser SDE Effect Compensation by Adaptive Tuning
    Publication number: 20160260579
    Abstract: Laser sub-divisional error (SDE) effect is compensated by using adaptive tuning. This compensated signal can be applied to position detection of stage in ebeam inspection tool, particularly for continuous moving stage.
    Type: Application
    Filed: March 3, 2016
    Publication date: September 8, 2016
    Applicant: Hermes Microvision Inc.
    Inventors: Ying Luo, KuoFeng Tseng, Zhonghua Dong
  • CONFORMAL NITRIDATION OF ONE OR MORE FIN-TYPE TRANSISTOR LAYERS
    Publication number: 20160190324
    Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.
    Type: Application
    Filed: March 3, 2016
    Publication date: June 30, 2016
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Wei Hua TONG, Tien-Ying LUO, Yan Ping SHEN, Feng ZHOU, Jun LIAN, Haoran SHI, Min-hwa CHI, Jin Ping LIU, Haiting WANG, Seung KIM
  • FORMS OF CO-CRYSTALS OF AGOMELATINE AND p TOLUENESULPHONIC ACID, A PROCESS FOR THEIR PREPARATION AND PHARMACEUTICAL COMPOSITIONS CONTAINING THEM
    Publication number: 20160168077
    Abstract: The present invention relates to new forms of co-crystals of agomelatine and p-toluenesulphonic acid, to a process for their preparation and to pharmaceutical compositions containing them. The co-crystals according to the invention have better solubility than agomelatine and are therefore more suitable for the preparation of pharmaceutical compositions. They also have better stability and purity and, moreover, are obtained by a simple process which does not include any difficult steps.
    Type: Application
    Filed: July 30, 2014
    Publication date: June 16, 2016
    Applicant: Les Laboratoires Servier
    Inventors: Hanbin SHAN, Yuhui SHEN, Ying LUO, Philippe LETELLIER, Michael LYNCH
  • COMPLEXES OF AGOMELATINE AND SULPHONIC ACIDS, A PROCESS FOR THEIR PREPARATION AND PHARMACEUTICAL COMPOSITIONS CONTAINING THEM
    Publication number: 20160159735
    Abstract: Complexes of agomelatine and sulphonic acids of formula (I): Medicinal products containing the same which are useful in treating disorders of the melatoninergic system.
    Type: Application
    Filed: July 28, 2014
    Publication date: June 9, 2016
    Inventors: Hanbin SHAN, Yuhui SHEN, Ying LUO, Philippe LETELLIER, Michael LYNCH
  • Conformal nitridation of one or more fin-type transistor layers
    Patent number: 9312145
    Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: April 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wei Hua Tong, Tien-Ying Luo, Yan Ping Shen, Feng Zhou, Jun Lian, Haoran Shi, Min-hwa Chi, Jin Ping Liu, Haiting Wang, Seung Kim
  • Polar plot to represent glucose sensor performance
    Patent number: 9307936
    Abstract: Disclosed are methods, apparatuses, etc. for providing a visual expression of the performance of one or more blood glucose sensors. In one particular example, a relative comparison of a rate of change sensor blood glucose and a rate of change in reference blood glucose may be expressed in a polar plot or graph. The polar plot or graph may then be generated onto a visual medium.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: April 12, 2016
    Assignee: Medtronic Minimed, Inc.
    Inventors: Rebecca K. Gottlieb, Ying Luo, Ning Yang, James Geoffrey Chase
  • Sensor systems having multiple probes and electrode arrays
    Patent number: 9215995
    Abstract: Embodiments of the invention provide amperometric analyte sensors having multiple related structural elements (e.g. sensor arrays comprising a working, counter and reference electrode) and algorithms designed for use with such sensors. While embodiments of the innovation can be used in a variety of contexts, typical embodiments of the invention include glucose sensors used in the management of diabetes.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: December 22, 2015
    Assignee: Medtronic MiniMed, Inc.
    Inventors: Rebecca K. Gottlieb, Chia-Hung Chiu, Meena Ramachandran, Nandita Dangui-Patel, Jefferson Rose, Ashwin K. Rao, Hsifu Wang, Ying Luo
  • Depositing an etch stop layer before a dummy cap layer to improve gate performance
    Patent number: 9209258
    Abstract: An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: December 8, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Feng Zhou, Tien-Ying Luo, Haiting Wang, Padmaja Nagaiah, Jean-Baptiste Laloe, Isabelle Pauline Ferain, Yong Meng Lee
  • Forming a gate by depositing a thin barrier layer on a titanium nitride cap
    Patent number: 9202697
    Abstract: A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: December 1, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tien-Ying Luo, Feng Zhou, Yan Ping Shen, Haiting Wang, Haoran Shi, Wei Hua Tong, Seung Kim, Yong Meng Lee
  • DEVICES AND METHODS OF FORMING FINFETS WITH SELF ALIGNED FIN FORMATION
    Publication number: 20150333067
    Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.
    Type: Application
    Filed: July 29, 2015
    Publication date: November 19, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jing WAN, Andy WEI, Lun ZHAO, Dae Geun YANG, Jin Ping LIU, Tien-Ying LUO, Guillaume BOUCHE, Mariappan HARIHARAPUTHIRAN, Churamani GAIRE
  • GLUCOSE SENSOR SIGNAL STABILITY ANALYSIS
    Publication number: 20150316559
    Abstract: Disclosed are methods, apparatuses, etc. for glucose sensor signal stability analysis. In certain example embodiments, a series of samples of at least one sensor signal that is responsive to a blood glucose level of a patient may be obtained. Based at least partly on the series of samples, at least one metric may be determined to assess an underlying trend of a change in responsiveness of the at least one sensor signal to the blood glucose level of the patient over time. A reliability of the at least one sensor signal to respond to the blood glucose level of the patient may be assessed based at least partly on the at least one metric assessing the underlying trend. Other example embodiments are disclosed herein.
    Type: Application
    Filed: July 10, 2015
    Publication date: November 5, 2015
    Inventors: Ying Luo, Rebecca K. Gottlieb, Meena Ramachandran, Chia-Hung Chiu, Nandita Dangui-Patel, Michael Kremliovsky, Jefferson Rose
  • Devices and methods of forming finFETs with self aligned fin formation
    Patent number: 9147696
    Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: September 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jing Wan, Andy Wei, Lun Zhao, Dae Geun Yang, Jin Ping Liu, Tien-Ying Luo, Guillaume Bouche, Mariappan Hariharaputhiran, Churamani Gaire
  • CONFORMAL NITRIDATION OF ONE OR MORE FIN-TYPE TRANSISTOR LAYERS
    Publication number: 20150255277
    Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 10, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Wei Hua TONG, Tien-Ying LUO, Yan Ping SHEN, Feng ZHOU, Jun LIAN, Haoran SHI, Min-hwa CHI, Jin Ping LIU, Haiting WANG, Seung KIM
  • DEPOSITING AN ETCH STOP LAYER BEFORE A DUMMY CAP LAYER TO IMPROVE GATE PERFORMANCE
    Publication number: 20150249136
    Abstract: An improved method for fabricating a semiconductor device is provided. The method includes: depositing a dielectric layer on a substrate; depositing a first cap layer on the dielectric layer; depositing an etch stop layer on the dielectric layer; and depositing a dummy cap layer on the etch stop layer to form a partial gate structure. Also provided is a partially formed semiconductor device. The partially formed semiconductor device includes: a substrate; a dielectric layer on the substrate; a first cap layer on the dielectric layer; an etch stop layer on the dielectric layer; and a dummy cap layer on the etch stop layer forming a partial gate structure.
    Type: Application
    Filed: March 3, 2014
    Publication date: September 3, 2015
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Feng ZHOU, Tien-Ying LUO, Haiting WANG, Padmaja NAGAIAH, Jean-Baptiste LALOE, Isabelle Pauline FERAIN, Yong Meng LEE
  • STABILISED AMORPHOUS FORM OF AGOMELATINE, A PROCESS FOR ITS PREPARATION AND PHARMACEUTICAL COMPOSITIONS CONTAINING IT
    Publication number: 20150238614
    Abstract: Stabilised amorphous form of the compound of formula (I): Medicaments
    Type: Application
    Filed: September 11, 2013
    Publication date: August 27, 2015
    Inventors: David Lafargue, Michael Lynch, Cécile Poirier, Philippe Letellier, Jean-Manuel Pean, Ying Luo, Hanbin Shan, Yuhui Shen
  • Glucose sensor signal stability analysis
    Patent number: 9101310
    Abstract: Disclosed are methods, apparatuses, etc. for glucose sensor signal stability analysis. In certain example embodiments, a series of samples of at least one sensor signal that is responsive to a blood glucose level of a patient may be obtained. Based at least partly on the series of samples, at least one metric may be determined to assess an underlying trend of a change in responsiveness of the at least one sensor signal to the blood glucose level of the patient over time. A reliability of the at least one sensor signal to respond to the blood glucose level of the patient may be assessed based at least partly on the at least one metric assessing an underlying trend. Other example embodiments are disclosed herein.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: August 11, 2015
    Assignee: Medtronic Minimed, Inc.
    Inventors: Ying Luo, Rebecca K. Gottlieb, Meena Ramachandran, Chia-Hung Chiu, Nandita Dangui-Patel, Michael Kremliovsky, Jefferson Rose
  • Method and apparatus for continuous analyte monitoring
    Patent number: 9008744
    Abstract: Embodiments of the invention provide analyte sensors and sensor systems such as amperometric glucose sensors used in the management of diabetes as well as optimized methods for monitoring analytes using such sensors and sensor systems.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: April 14, 2015
    Assignee: Medtronic MiniMed, Inc.
    Inventors: Jefferson Rose, Ashwin K. Rao, Ning Yang, Chia-Hung Chiu, Ying Luo, Rebecca K. Gottlieb
  • DEVICES AND METHODS OF FORMING FINFETS WITH SELF ALIGNED FIN FORMATION
    Publication number: 20150091094
    Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 2, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Jing WAN, Andy WEI, Lun ZHAO, Dae Geun YANG, Jin Ping LIU, Tien-Ying LUO, Guillaume BOUCHE, Mariappan HARIHARAPUTHIRAN, Churamani GAIRE
  • Dual high-K oxides with SiGe channel
    Patent number: RE45955
    Abstract: A method and apparatus are described for integrating dual gate oxide (DGO) transistor devices (50, 52) and core transistor devices (51, 53) on a single substrate (15) having a silicon germanium channel layer (21) in the PMOS device areas (112, 113), where each DGO transistor device (50, 52) includes a metal gate (25), an upper gate oxide region (60, 84) formed from a second, relatively higher high-k metal oxide layer (24), and a lower gate oxide region (58, 84) formed from a first relatively lower high-k layer (22), and where each core transistor device (51, 53) includes a metal gate (25) and a core gate dielectric layer (72, 98) formed from only the second, relatively higher high-k metal oxide layer (24).
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: March 29, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Tien Ying Luo, Gauri V. Karve, Daniel K. Tekleab