Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.

Abstract: A HVJT structure of HVIC includes P-type substrate. Epitaxial layer is formed on the substrate. N-type doped structure is formed in the epitaxial layer, contacting with the substrate. P-type doped structure is in the N-type doped structure connecting with anode. The substrate, the N-type doped structure and the P-type doped structure form a PNP path along a perpendicular direction to the substrate, wherein NP provide bootstrap diode function and surround the high-side circuit at a horizontal direction. N-type cathode structure is in the epitaxial layer. N-type epitaxial doped region contacts with the substrate, between the PNP path and the N-type cathode structure, also surrounding the high-side circuit. Gate structure is over the N-type epitaxial doped region, between the P-type doped structure and N-type cathode structure. P-type base doped structure is in the epitaxial layer adjacent to the N-type doped structure, to provide a substrate voltage to the substrate.

Abstract: A method for manufacturing an electrode including the following steps is provided. A conductive layer is formed on a base material. A radio frequency physical vapor deposition (RF PVD) transition metal compound layer is formed on the conductive layer by using a RF PVD. A sacrificial layer is formed on the RF PVD transition metal compound layer. A planarization process is performed to remove the sacrificial layer and a portion of the RF PVD transition metal compound layer.

Abstract: A semiconductor apparatus includes a high side region and a low side region, wherein the high side region includes semiconductor devices, and those semiconductor devices have at least two devices with different operating voltages. In the high side region, at least one isolation structure is located between the devices with different operating voltages to prevent short circuit between the devices.

Abstract: A cell culture module, a cell culture system and a cell culture method are provided. The cell culture module includes a casing, a first fixer, a second fixer and a sheet-shaped carrier member. The casing has a chamber and at least one inlet/outlet. The inlet/outlet communicates with the chamber. The first fixer is fixed to the casing and located in the chamber. The second fixer is disposed in the chamber and is movable relative to the first fixer. The sheet-shaped carrier member is formed by arranging a plurality of cell culture carriers, and two opposite ends of the sheet-shaped carrier member are respectively fixed to the first fixer and the second fixer. The sheet-shaped carrier member is in an open state or a folded state according to a variation in a distance between the first fixer and the second fixer due to a movement of the second fixer.

Abstract: Provided is a semiconductor device including a substrate having a P-type conductivity, a buried layer having an N-type conductivity, an NPN bipolar junction transistor (BJT), and a first well region having the P-type conductivity. The buried layer is located on the substrate. The NPN BJT is located on the buried layer. The first well region is located between the buried layer and the NPN BJT. The NPN BJT is separated from the buried layer by the first well region.

Abstract: A semiconductor device including a substrate, a metal-oxide-semiconductor field-effect transistor (MOSFET), and a plurality of junction gate field-effect transistors (JFETs) connected in parallel is provided. The MOSFET is disposed on a substrate. The MOSFET includes a source region, a drain region, and a gate structure disposed between the source region and the drain region. The JFETs and the MOSFET are connected in series. Each of the JFETs laterally extends between the source region and the drain region.

Abstract: A semiconductor device including a substrate of a first conductivity type, a metal-oxide-semiconductor-field-effect transistor (MOSFET), junction gate field-effect transistors (JFETs), an isolation structure, and a buried layer of a second conductivity type is provided. The MOSFET is located on the substrate and has a first epitaxial layer of the second conductivity type. The JFET is located on the substrate and has a second epitaxial layer of the second conductivity type. The isolation structure is located between the MOSFET and the JFET to separate the first epitaxial layer from the second epitaxial layer. The buried layer is located between the MOSFET and the substrate. The buried layer extends from below the MOSFET to below the isolation structure and below the JFET, so as to electrically connect the MOSFET to the first JFET.

Abstract: A cell culture carrier module and a cell culture system having the same are provided. A cell tank and a culture medium module respectively communicate with the carrier module. The carrier module includes a reactor, a first fixer, a second fixer and a plurality of cell culture carriers. The reactor has a chamber and at least one inlet/outlet. The inlet/outlet communicates with the chamber. The first fixer is fixed to the reactor and located in the chamber. The second fixer is disposed in the chamber and is movable relative to the first fixer. Two ends of each cell culture carrier are fixed to the first fixer and the second fixer, respectively. The cell culture carriers are in an untwisted state or a twisted state according to a variation in a distance between the first fixer and the second fixer due to a movement of the second fixer.

Abstract: A semiconductor apparatus includes a high side region and a low side region, wherein the high side region includes semiconductor devices, and those semiconductor devices have at least two devices with different operating voltages. In the high side region, at least one isolation structure is located between the devices with different operating voltages to prevent short circuit between the devices.

Abstract: A semiconductor device including a substrate of a first conductivity type, a metal-oxide-semiconductor-field-effect transistor (MOSFET), junction gate field-effect transistors (JFETs), an isolation structure, and a buried layer of a second conductivity type is provided. The MOSFET is located on the substrate and has a first epitaxial layer of the second conductivity type. The JFET is located on the substrate and has a second epitaxial layer of the second conductivity type. The isolation structure is located between the MOSFET and the JFET to separate the first epitaxial layer from the second epitaxial layer. The buried layer is located between the MOSFET and the substrate. The buried layer extends from below the MOSFET to below the isolation structure and below the JFET, so as to electrically connect the MOSFET to the first JFET.

Abstract: A HVJT structure of HVIC includes P-type substrate. Epitaxial layer is formed on the substrate. N-type doped structure is formed in the epitaxial layer, contacting with the substrate. P-type doped structure is in the N-type doped structure connecting with anode. The substrate, the N-type doped structure and the P-type doped structure form a PNP path along a perpendicular direction to the substrate, wherein NP provide bootstrap diode function and surround the high-side circuit at a horizontal direction. N-type cathode structure is in the epitaxial layer. N-type epitaxial doped region contacts with the substrate, between the PNP path and the N-type cathode structure, also surrounding the high-side circuit. Gate structure is over the N-type epitaxial doped region, between the P-type doped structure and N-type cathode structure. P-type base doped structure is in the epitaxial layer adjacent to the N-type doped structure, to provide a substrate voltage to the substrate.

Abstract: A semiconductor device including a substrate, a metal-oxide-semiconductor field-effect transistor (MOSFET), and a plurality of junction gate field-effect transistors (JFETs) connected in parallel is provided. The MOSFET is disposed on a substrate. The MOSFET includes a source region, a drain region, and a gate structure disposed between the source region and the drain region. The JFETs and the MOSFET are connected in series. Each of the JFETs laterally extends between the source region and the drain region.

Abstract: Provided is a semiconductor device including a substrate having a P-type conductivity, a buried layer having an N-type conductivity, an NPN bipolar junction transistor (BJT), and a first well region having the P-type conductivity. The buried layer is located on the substrate. The NPN BJT is located on the buried layer. The first well region is located between the buried layer and the NPN BJT. The NPN BJT is separated from the buried layer by the first well region.

Abstract: Rhodamine B derivative selectively chelates Sn2+ to act as a fluorescent probe.

Abstract: A method includes forming a first nitride layer on a semiconductor substrate, forming a first oxide layer on the first nitride layer, forming a first trench through the first oxide layer, the first nitride layer and a portion of the semiconductor substrate, forming a first spacer on a sidewall of the first trench, forming a second trench in the semiconductor substrate by using the first spacer as a mask, forming a third trench, forming a second oxide layer in the second trench, wherein the second oxide layer laterally extends into the semiconductor substrate and under the first spacer, forming a second spacer on a sidewall of the third trench, and removing a portion of the first nitride layer and a portion of the semiconductor substrate by etching and using the second spacer as a mask to form a fin structure on the second oxide layer.

Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.

Abstract: A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.

Abstract: An embodiment semiconductor device includes a first conductive feature in a dielectric layer and a second conductive feature over the dielectric layer and electrically connected to the first conductive feature. The second conductive feature includes a dual damascene structure and further includes a top portion within both a line portion and a via portion of the second conductive feature and a bottom portion in the via portion of the second conductive feature. The bottom portion comprises a different conductive material than the top portion, and a thickness of the bottom portion is at least about twenty percent of a total thickness of the via portion of the second conductive feature.

Abstract: A method for manufacturing an electrode including the following steps is provided. A conductive layer is formed on a base material. A radio frequency physical vapor deposition (RF PVD) transition metal compound layer is formed on the conductive layer by using a RF PVD. A sacrificial layer is formed on the RF PVD transition metal compound layer. A planarization process is performed to remove the sacrificial layer and a portion of the RF PVD transition metal compound layer.