Patents by Inventor Yoichiro Kurita
Yoichiro Kurita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160268232Abstract: According to one embodiment, a semiconductor device includes a laminate including a plurality of semiconductor chips and having a first width, at least part of the semiconductor chips including an electrode extending through the semiconductor chip, the semiconductor chips being stacked and connected to each other via the electrode; a silicon substrate provided on a first surface of the laminate and having a second width larger than the first width; a wiring layer provided on a second surface of the laminate; and a resin provided around the laminate.Type: ApplicationFiled: August 28, 2015Publication date: September 15, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yoichiro KURITA
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Patent number: 9406602Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.Type: GrantFiled: January 27, 2015Date of Patent: August 2, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
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Patent number: 9396998Abstract: According to one embodiment, the first resin layer is provided on the first face of the upper layer chip. The first interconnect layer is electrically connected to the upper layer chip. The second resin layer extends into a region outside chip. The region is outer side of a side face of the upper layer chip. The second interconnect layer is provided in the second resin layer. The second interconnect layer is connected to the first interconnect layer and extending into the region outside chip. The lower layer chip is mounted on the surface side of the first resin layer, and is connected to the first interconnect layer. The first sealing resin covers the upper layer chip.Type: GrantFiled: September 5, 2014Date of Patent: July 19, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoichiro Kurita, Hirokazu Ezawa, Kazushige Kawasaki, Satoshi Tsukiyama
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Publication number: 20160204092Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.Type: ApplicationFiled: March 17, 2016Publication date: July 14, 2016Inventor: Yoichiro KURITA
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Publication number: 20160126218Abstract: According to one embodiment, there is provided a bonding method of a semiconductor chip. The bonding method includes arranging an activated front surface of a semiconductor chip and an activated front surface of a substrate so as to face each other with a back surface of the semiconductor chip attached to a sheet. The bonding method includes pushing the back surface of the semiconductor chip through the sheet to closely attach the activated front surface of the semiconductor chip and the activated front surface of the substrate. The bonding method includes stripping the sheet from the back surface of the semiconductor chip while maintaining a state in which the activated front surface of the semiconductor chip is closely attached to the activated front surface of the substrate.Type: ApplicationFiled: May 12, 2015Publication date: May 5, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Yoichiro KURITA
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Patent number: 9324699Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.Type: GrantFiled: October 27, 2014Date of Patent: April 26, 2016Assignee: RENESAS ELECTONICS CORPORATIONInventor: Yoichiro Kurita
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Publication number: 20160079184Abstract: A semiconductor device includes a first semiconductor chip including an inorganic protective film, a second semiconductor chip including an organic protective film and a re-wiring layer, the second semiconductor chip being electrically connected to the first semiconductor chip through a through-silicon via and a bump connection, a third semiconductor chip including an inorganic protective film, the third semiconductor chip being electrically connected to the second semiconductor chip through the re-wiring layer and a bump connection, a first resin layer filled between the first semiconductor chip and the second semiconductor chip, the first resin layer being in contact with the inorganic protective film, and a second resin layer filled between the second semiconductor chip and the third semiconductor chip, the second resin layer being in contact with the organic protective film and the inorganic protective film.Type: ApplicationFiled: March 2, 2015Publication date: March 17, 2016Inventors: Satoshi TSUKIYAMA, Hideko MUKAIDA, Yoichiro KURITA
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Publication number: 20160071604Abstract: According to one embodiment, a semiconductor memory device includes: a first component including a controller which issues an instruction complying with a NAND interface; and a second component including a first NAND flash memory which is controlled by the instruction, the second component being removable from the first component.Type: ApplicationFiled: March 9, 2015Publication date: March 10, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoichiro KURITA, Hiroyuki SUTO, Fuminori KIMURA
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Publication number: 20150262989Abstract: A semiconductor device includes a first chip, a second chip stacked on the first chip, and a third chip stacked on the second chip. The second chip includes a second semiconductor layer having a second circuit surface facing the first wiring layer and a second rear surface opposite to the second circuit surface, a second wiring layer provided on the second circuit surface and connected to a first wiring layer of the first chip, and a second electrode extending through the second semiconductor layer and connected to the second wiring layer. The third chip includes a third semiconductor layer having a third circuit surface and a third rear surface facing the second chip, a third wiring layer provided on the third circuit surface, and a third electrode extending through the third semiconductor layer, connected to the third wiring layer and connected to the second electrode through bumps.Type: ApplicationFiled: September 2, 2014Publication date: September 17, 2015Inventors: Kazushige KAWASAKI, Yoichiro KURITA
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Publication number: 20150262877Abstract: According to one embodiment, the first resin layer is provided on the first face of the upper layer chip. The first interconnect layer is electrically connected to the upper layer chip. The second resin layer extends into a region outside chip. The region is outer side of a side face of the upper layer chip. The second interconnect layer is provided in the second resin layer. The second interconnect layer is connected to the first interconnect layer and extending into the region outside chip. The lower layer chip is mounted on the surface side of the first resin layer, and is connected to the first interconnect layer. The first sealing resin covers the upper layer chip.Type: ApplicationFiled: September 5, 2014Publication date: September 17, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoichiro KURITA, Hirokazu EZAWA, Kazushige KAWASAKI, Satoshi TSUKIYAMA
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Publication number: 20150137348Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.Type: ApplicationFiled: January 27, 2015Publication date: May 21, 2015Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
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Publication number: 20150069596Abstract: According to one embodiment, a semiconductor device includes a metal plate, a plurality of semiconductor chips, an insulation layer, a wiring layer, external connection terminals and a sealing resin portion. The metal plate includes a first surface and the plurality of semiconductor chips are laminated on a second surface of the metal plate. The insulation layer and the wiring layer are provided on the semiconductor chips. The external connection terminals are provided on the insulation layer and the wiring layer. The sealing resin portion seals the plurality of semiconductor chips while exposing the first surface of the metal plate. At least one pair of opposing outer peripheral surfaces of the metal plate are covered with the sealing resin portion.Type: ApplicationFiled: February 26, 2014Publication date: March 12, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazushige KAWASAKI, Yoichiro KURITA, Satoshi TSUKIYAMA, Masayuki MIURA
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Patent number: 8975750Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.Type: GrantFiled: August 8, 2014Date of Patent: March 10, 2015Assignee: Renesas Electronics CorporationInventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
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Publication number: 20150041978Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.Type: ApplicationFiled: October 27, 2014Publication date: February 12, 2015Inventor: Yoichiro KURITA
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Patent number: 8916976Abstract: First semiconductor element 1 being buried in first insulating material 2; second semiconductor element 5 being covered by second insulating material 6; connection electrode 4 being buried in first insulating material 2 arranged between circuit surface of first semiconductor element 1 and circuit surface of second semiconductor element 5; external connection terminal 8 being arranged on lower surface of first insulating material 2 facing in the same direction as lower surface of first semiconductor element 1 opposite to circuit surface thereof; connection electrode 4 forming a part of path for electrically connecting circuit surface of first semiconductor element 1 and circuit surface of second semiconductor element 5 to each other; first semiconductor element 1 and external connection terminal 8 being electrically connected to each other by way of wire 3 and via 7 passing through region of insulating layer other than region thereof burying connection electrode 4.Type: GrantFiled: March 21, 2008Date of Patent: December 23, 2014Assignee: Renesas Electronics CorporationInventors: Masamoto Tago, Yoichiro Kurita
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Publication number: 20140346681Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.Type: ApplicationFiled: August 8, 2014Publication date: November 27, 2014Inventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
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Patent number: 8890305Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.Type: GrantFiled: August 21, 2013Date of Patent: November 18, 2014Assignee: Renesas Electronics CorporationInventor: Yoichiro Kurita
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Patent number: 8823174Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.Type: GrantFiled: December 17, 2013Date of Patent: September 2, 2014Assignee: Renesas Electronics CorporationInventors: Yoichiro Kurita, Masaya Kawano, Koji Soejima
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Publication number: 20140103524Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.Type: ApplicationFiled: December 17, 2013Publication date: April 17, 2014Applicant: Renesas Electronics CorporationInventors: Yoichiro KURITA, Masaya KAWANO, Koji SOEJIMA
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Patent number: 8685796Abstract: The electronic device includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of the second interconnect layer is smaller in area than the opposite end face. The via plug is exposed on the surface of the first interconnect layer facing the second interconnect layer. An insulating resin forming the first interconnect layer is higher in thermal decomposition temperature than an insulating resin forming the second interconnect layer.Type: GrantFiled: September 18, 2007Date of Patent: April 1, 2014Assignee: Renesas Electronics CorporationInventors: Yoichiro Kurita, Koji Soejima, Masaya Kawano