Abstract: The semiconductor chip 1 has a semiconductor substrate 10. In the present embodiment, the semiconductor substrate 10, which is an SOI substrate, is constituted by comprising a support substrate 12, an insulating layer 14 formed on the support substrate 12 with a layered structure, and a silicon layer 16 formed on the insulating layer 14 with the layered structure. The semiconductor substrate 10 has a circuit forming region A1 provided in the silicon layer 16. An insulating region 18 is provided on the semiconductor substrate 10. The insulating region 18 is provided so as to surround the entire side face of the circuit forming region A1.

Abstract: A thin, planar semiconductor device having electrodes on both surfaces is disclosed. This semiconductor device is provided with an IC chip and a wiring layer having one side that is electrically connected to surface electrodes of the IC chip. On this surface of the wiring layer, conductive posts are provided on wiring of the wiring layer, and an insulating resin covers all portions not occupied by the IC chip and conductive posts. The end surfaces of the conductive posts are exposed from the insulating resin and are used as first planar electrodes. In addition, a resist layer is formed on the opposite surface of the wiring layer. Exposed portions are formed in the resist layer to expose desired wiring portions of the wiring layer. These exposed portions are used as second planar electrodes. Stacking semiconductor devices of this construction enables an improvement in the integration of semiconductor integrated circuits.

Abstract: A flip-chip type semiconductor device includes a semiconductor substrate. A plurality of electrode terminals are provided and arranged on a top surface of the semiconductor substrate, a sealing resin layer is formed on the top surface of the semiconductor substrate such that the electrode terminals are completely covered with the sealing resin layer.

Abstract: A manufacturing method for manufacturing an electronic device includes a first electronic component and a second electronic component; and a bond part for the first electronic component joined to another bond part for the second electronic component. In a first process of this manufacturing method, the metallic bond part for the first electronic component is placed directly against the metallic bond part for the second electronic component, pressure is applied to the first electronic component and the second electronic component and, after metallically joining the above two bond parts, the pressure applied to the first electronic component and the second electronic component is released. In a second process in the manufacturing method, a clamping member affixes the relative positions of the joined first electronic component and second electronic component, and heats the first electronic component and the second electronic component to maintain a specified temperature.

Abstract: The method of manufacturing an electronic circuit device according to an embodiment of the present invention includes preparing an interconnect substrate 10 including an interconnect 14 and an electrode pad 16 integrally formed with the interconnect 14; preparing an electronic circuit chip 20 including a solder electrode 22; and melting the solder electrode 22 and connecting it to the electrode pad 16, thus connecting the interconnect substrate 10 and the electronic circuit chip 20. A first metal material, exposed in the surface of the electrode pad 16 opposite to an insulating resin layer 12 and constituting the electrode pad 16, has higher free energy for forming an oxide than a second metal material exposed in the surface of the interconnect 14 opposite to the insulating resin layer 12 and constituting the interconnect 14.

Abstract: A flip-chip type semiconductor device includes a semiconductor substrate. A plurality of electrode terminals are provided and arranged on a top surface of the semiconductor substrate, a sealing resin layer is formed on the top surface of the semiconductor substrate such that the electrode terminals are completely covered with the sealing resin layer.

Abstract: A semiconductor device-composing substrate 10 has a support base 12, an interconnect layer 14 including interconnects 13, and an insulating resin layer 16. The semiconductor device-composing substrate 10 also has a mounting region D1 on which a semiconductor chip 30 is to be mounted. The insulating resin layer 16 is formed on the interconnect layer 14. Chip-connecting electrodes 17, external electrode pads 18 and the resin stopper patterns 19 are formed in the insulating resin layer 16. The chip-connecting electrodes 17 are provided in the mounting region D1. The external electrode pads 18 are provided outside the mounting region D1. The resin stopper patterns 19 are provided between the mounting region D1 and the external electrode pads 18.

Abstract: An oxide layer and a metal layer composed of a gold- or platinum-group metal are formed in the stated order on a substrate. A wiring body having a wiring layer, insulating layer, via, and electrode is formed on the metal layer. A semiconductor element is then connected as a flip chip via solder balls on the wiring body electrode, and underfill is introduced between the semiconductor element and the wiring body. Subsequently, a sealing resin layer is formed so as to cover the semiconductor element and the surface of the wiring body on which the semiconductor element is mounted, thus producing a semiconductor package. A high-density, detailed, thin semiconductor package can thereby be realized.

Abstract: A semiconductor element (1) includes a semiconductor substrate (11) and a conductive post portion (121) protruding from the semiconductor substrate (11). The conductive post portion (121) is provided to the semiconductor substrate (11) and is free from a recessed portion recessed in a direction intersecting with a protruding direction of the conductive post portion (121) on an outer surface extending from a distal end to a proximal end on a semiconductor substrate (11) side.

Abstract: Aimed at providing a semiconductor device improved in reliability of bonding and yield of products, even when semiconductor chips having through electrodes are used, the semiconductor device of the present invention has a substrate; a stack placed on the substrate, and composed of a plurality of semiconductor chips (first semiconductor chip and second semiconductor chip), each having through electrodes, stacked while placing bumps connected to the through electrodes in between; and a reinforcing chip (semiconductor chip) provided on the stack specifically on the surface thereof opposite to the substrate-side surface, or between the substrate and the stack, wherein thickness of the reinforcing chip is larger than the thickest semiconductor chip out of the plurality of semiconductor chips.

Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

Abstract: A method of manufacturing a semiconductor device including a PMOS transistor and a NMOS transistor is described. The method facilitates obtaining a FUSI phase of a suitable composition for the NMOS transistor and the PMOS transistor respectively, with fewer mask layers and through a fewer number of manufacturing steps.

Abstract: First semiconductor element 1 being buried in first insulating material 2; second semiconductor element 5 being covered by second insulating material 6; connection electrode 4 being buried in first insulating material 2 arranged between circuit surface of first semiconductor element 1 and circuit surface of second semiconductor element 5; external connection terminal 8 being arranged on lower surface of first insulating material 2 facing in the same direction as lower surface of first semiconductor element 1 opposite to circuit surface thereof; connection electrode 4 forming a part of path for electrically connecting circuit surface of first semiconductor element 1 and circuit surface of second semiconductor element 5 to each other; first semiconductor element land external connection terminal 8 being being electrically connected to each other by way of wire 3 and via 7 passing through region of insulating layer other than region thereof burying connection electrode 4.

Abstract: The semiconductor device 1 includes interconnect layers 10, 20, an IC chip 30, via plugs 42, 44, a seal resin 50, and solder balls 60. The interconnect layer 10 includes a via plug 42. An end face of the via plug 42 on the side of the interconnect layer 20 is smaller in area than the opposite end face, i.e. the end face on the side of the IC chip 30. An end face of the via plug 44 on the side of the interconnect layer 10 is smaller in area than the opposite end face, i.e. the end face on the side of the solder balls 60. The thermal decomposition temperature of the insulating resin 14 constituting the interconnect layer 10 is higher than that of the insulating resin 24 constituting the interconnect layer 20.

Abstract: A thin, planar semiconductor device having electrodes on both surfaces is disclosed. This semiconductor device is provided with an IC chip and a wiring layer having one side that is electrically connected to surface electrodes of the IC chip. On this surface of the wiring layer, conductive posts are provided on wiring of the wiring layer, and an insulating resin covers all portions not occupied by the IC chip and conductive posts. The end surfaces of the conductive posts are exposed from the insulating resin and are used as first planar electrodes. In addition, a resist layer is formed on the opposite surface of the wiring layer. Exposed portions are formed in the resist layer to expose desired wiring portions of the wiring layer. These exposed portions are used as second planar electrodes. Stacking semiconductor devices of this construction enables an improvement in the integration of semiconductor integrated circuits.

Abstract: A first electronic circuit component and a second electronic circuit component are electrically connected to an electro-conductive member via a first solder and a second solder, respectively. The electro-conductive member is formed in a resin film. The electro-conductive member is configured as containing a second diffusion barrier metal film. The second diffusion barrier metal film prevents diffusion of the second solder. Between the electro-conductive member and the first solder, a first diffusion barrier metal film is provided. The first diffusion barrier metal film prevents diffusion of the first solder. On the first surface of the resin film and on the electro-conductive member, an adhesive metal film is formed so as to contact with the resin film and the electro-conductive member. The adhesive metal film has stronger adhesiveness to the resin film than either of those of the first solder and the first diffusion barrier metal film.

Abstract: Provided is a semiconductor device including an interconnect substrate, a transmission line which is formed on the interconnect substrate, and a circuit component which is mounted over the interconnect substrate and has a ground plane. The transmission line includes a first portion and a second portion that is connected to the first portion. The first portion and the ground plane constitute a microstrip line. The second portion and ground line constitute a coplanar line.

Abstract: Disclosed are a bonding method for a semiconductor chip, which employs an ultrasonic bonding scheme that prevents wear-out of the top surface of a mount tool and ensures both high reliability and high productivity, and a bonding apparatus which is used to carry out the method. The bonding apparatus and method are provided with means for suppressing generation of a sliding friction. The apparatus and method execute a bonding process by controlling vibration-axial directional holding force and inertial force based on information given from control management means to thereby maintain a relationship of (vibration-axial directional holding force)>(die shear strength)+(inertial force) while applying an ultrasonic vibration to a region which is subjected to bonding.

Abstract: The electronic device includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of the second interconnect layer is smaller in area than the opposite end face. The via plug is exposed on the surface of the first interconnect layer facing the second interconnect layer. An insulating resin forming the first interconnect layer is higher in thermal decomposition temperature than an insulating resin forming the second interconnect layer.

Abstract: The electronic device includes a first interconnect layer and a second interconnect layer. The second interconnect layer is provided on the lower surface of the first interconnect layer. The first interconnect layer includes a via plug (first conductive plug). An end face of the via plug on the side of the second interconnect layer is smaller in area than the opposite end face. The via plug is exposed on the surface of the first interconnect layer facing the second interconnect layer. An insulating resin forming the first interconnect layer is higher in thermal decomposition temperature than an insulating resin forming the second interconnect layer.